Abstract: The nitride-based semiconductor light-emitting device and manufacturing method thereof are disclosed: the nitride-based semiconductor light-emitting device includes a reflective layer formed on a support substrate, a p-type nitride-based semiconductor layer, a light-emitting layer and an n-type nitride-based semiconductor layer successively formed on the reflective layer, wherein irregularities are formed on a light extracting surface located above the n-type nitride-based semiconductor layer.

Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

Abstract: A backside illuminated imaging pixel with improved angular response includes a semiconductor layer having a front and a back surface. The imaging pixel also includes a photodiode region formed in the semiconductor layer. The photodiode region includes a first and a second n-region. The first n-region has a centerline projecting between the front and back surfaces of the semiconductor layer. The second n-region is disposed between the first n-region and the back surface of the semiconductor layer such that the second n-region is offset from the centerline of the first n-region.

Abstract: A light emission device manufactured by a method of forming a curved surface having a radius of curvature to the upper end of an insulator 19, exposing a portion of the first electrode 18c to form an inclined surface in accordance with the curved surface, and applying etching so as to expose the first electrode 18b in a region to form a light emission region, in which emitted light from the layer containing the organic compound 20 is reflected on the inclined surface of the first electrode 18c to increase the total take-out amount of light in the direction of an arrow shown in FIG.

Abstract: A semiconductor device and a method of fabricating the same include a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region, and contact electrodes including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to source/drain regions. The first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode. The gate electrode can be easily connected to the contact electrode, the high-concentration region can be disposed only on the channel region, making it possible to maximize overall performance of the semiconductor device.

Abstract: A sensing device includes an optical cavity having two substantially opposed reflective surfaces. At least one nanowire is operatively disposed in the optical cavity. A plurality of metal nanoparticles is established on the at least one nanowire.

Abstract: In a light emitting package (8), at least one light emitting chip (12, 14, 16, 18) is supported by a board (10). A light transmissive encapsulant (30) is disposed over the at least one light emitting chip and over a footprint area (32) of the board. A light transmissive generally conformal shell (40) is disposed over the encapsulant and has an inner surface (44) spaced apart by an air gap (G) from, and generally conformal with, an outer surface (34) of the encapsulant. At least one phosphor (50) is disposed on or embedded in the conformal shell to output converted light responsive to irradiation by the at least one light emitting chip. A thermally conductive filler material disposed in the generally conformal shell (40) is effective to enhance a thermal conductivity of the composite shell material to a value higher than 0.3 W/(m·K).

Abstract: The present invention provides a display device which can prevent the deterioration of a transparent conductive film attributed to a cell reaction without pushing up a cost of a film forming device. The display device includes a first conductive layer which is formed of a transparent conductive film containing indium oxide as a main component, a conductive background layer which is formed on the first conductive layer, a second conductive layer which is formed of a film containing Al as a main component on the background layer, and a third conductive layer which is formed of the same material as the second conductive layer on the second conductive layer. On an interface between the second conductive layer and the third conductive layer, positions of grain boundaries are arranged discontinuously. Further, the background layer is a film which contains any one of Mo, Ti and Ta as a main component. Still further, the third conductive layer is used as a reflective electrode.

Abstract: In order to prevent irreversible deformation of column-shaped spacers which retain the gap between a pair of substrates between which the liquid crystal layer of a liquid crystal display device is interposed, spacers which assist in preventing such irreversible deformation are newly provided. According to the invention, two or more kinds of spacers which differ in height from a reference surface are disposed on one of the pair of substrates. In addition, a step pattern with which the spacers are to come into contact is formed in advance on the other of the pair of substrates so that the heights of the spacers can be made different.

Abstract: A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

Abstract: A wafer bonded composite structure is provided for matching a coefficient of thermal expansion of a first semiconductor chip to a coefficient of thermal expansion of a second semiconductor chip in order to provide a thermally matched hybridized semiconductor chip assembly. The wafer bonded composite structure includes a first semiconductor chip having a top and a bottom surface. The first semiconductor chip has a coefficient of thermal expansion which is less than the coefficient of thermal expansion of the second semiconductor chip. Preferably, the first semiconductor chip is an readout integrated circuit (ROIC) and the second semiconductor chip is an infrared detector chip. Further, the wafer bonded composite structure also includes a substrate wafer bonded to a bottom surface of the first semiconductor chip to form the wafer bonded composite structure itself.

Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.

Abstract: A nitride semiconductor light emitting device has high internal quantum efficiency but low operating voltage. The nitride semiconductor light emitting device includes an n-nitride semiconductor layer; an active layer of multi-quantum well structure formed on the n-nitride semiconductor layer, and having a plurality of quantum well layers and a plurality of quantum barrier layers; and a p-nitride semiconductor layer formed on the active layer. One of the quantum well layers adjacent to the n-nitride semiconductor layer has an energy band gap greater than that of another one of the quantum well layers adjacent to the p-nitride semiconductor layer.

Abstract: A top-emitting organic light emitting device having an improved pixel electrode layout for decreasing photo-leakage of a thin film transistor and enhancing an aperture ratio is provided. In the top-emitting organic light emitting device, the pixel electrode is designed to have the maximum size allowed by a layout design rule. Further, the pixel electrode is formed to overlap all the thin film transistors below.

Abstract: A semiconductor light emitting device comprises: a substrate; a semiconductor stacked structure; a first electrode; a second electrode; and a reflective film. The substrate has a top face and a rear face electrode forming portion opposed thereto, and is translucent to light in a first wavelength band. The rear face electrode forming portion is surrounded by a rough surface. The semiconductor stacked structure is provided on the top face of the substrate and includes an active layer that emits light in the first wavelength band. The first electrode is provided on the semiconductor stacked structure, and the second electrode is provided on the rear face electrode forming portion. The reflective film is coated on at least a portion of the rough surface.

Abstract: An exemplary optical lens (300) includes a top surface (301), a base portion (304) opposite to the top surface, and a peripheral side surface defining a first refractive portion (302). The top surface is a generally funnel-shaped top surface. The first refractive portion is corrugated with a plurality of protruding ridge structures, and each of the ridge structures includes a refractive surface (3021). An exemplary light emitting device incorporating the optical lens is also provided.

Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: A CMOS image sensor is provided. The CMOS image sensor can include: a plurality of photodiodes formed on a semiconductor substrate; an interlayer dielectric layer formed on an entire surface of the semiconductor substrate having the plurality of photodiodes; color filter layers including multi-layered blue color filter layers formed on the interlayer dielectric layer corresponding to respective photodiodes of the plurality of photodiodes; a planarization layer formed on the semiconductor substrate having the color filter layers; and microlenses formed on the planarization layer.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.