Patents Examined by Alan E. Schiavelli
  • Patent number: 4628588
    Abstract: A molybdenum mask is used instead of a photoresist mask in defining and etching an oxide-encapsulated molybdenum gate in a VLSI manufacturing method. The molybdenum mask is first defined by a photoresist mask, then the photoresist is removed, leaving the molybdenum mask. A long over etch can then be tolerated so that oxide filaments can be avoided; this would be otherwise unreliable due to damage to photoresist during the over etch.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: December 16, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: James M. McDavid
  • Patent number: 4599787
    Abstract: A light emitting semiconductor device having a double hetero junction structure in which oscillation in a single lateral mode is stably effected. A stair-shaped step part is formed in a stripe shape upon the surface of a substrate. A current blocking layer of an opposite conductivity type is formed over the semiconductor substrate with a thickness such that the current blocking layer is interrupted along the upper edge of the stair-shaped step part to form a break area therein which acts as a current concentration region. Over the current blocking layer and break area are formed a lower clad layer, an active layer, an upper clad layer, and an ohmic contact layer.
    Type: Grant
    Filed: November 25, 1981
    Date of Patent: July 15, 1986
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yukihiro Sasatani
  • Patent number: 4599790
    Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess.
    Type: Grant
    Filed: January 30, 1985
    Date of Patent: July 15, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Bumman Kim, Paul Saunier
  • Patent number: 4592131
    Abstract: A method for manufacturing a resin-sealed semiconductor device wherein after a semiconductor pellet is sealed to a leadframe with a resin, outer leads projected from the leadframe and adhered with burrs are collapsed by their upper or upper and lower corners and then the burrs are removed by blasting.
    Type: Grant
    Filed: December 18, 1984
    Date of Patent: June 3, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Deie
  • Patent number: 4587712
    Abstract: A vertical channel junction gate electric field controlled device (e.g., a field effect transistor, or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves, generally on the upper surface of the base region layer, are upper electrode regions, for example, source electrode regions or cathode electrode regions. Recessed in the grooves are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions in the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection.
    Type: Grant
    Filed: January 17, 1985
    Date of Patent: May 13, 1986
    Assignee: General Electric Company
    Inventor: Bantval J. Baliga
  • Patent number: 4587711
    Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.
    Type: Grant
    Filed: August 6, 1984
    Date of Patent: May 13, 1986
    Assignee: Rockwell International Corporation
    Inventor: Gordon C. Godejahn, Jr.
  • Patent number: 4587719
    Abstract: A method of forming a flexible array of circuit elements and electrical contacts where parallel lines of conductors joined by short perpendicular line of conductors are folded both about an axis parallel to the perpendicular line of elements and about an axis parallel to parallel lines thereby forming a linear array.
    Type: Grant
    Filed: June 5, 1984
    Date of Patent: May 13, 1986
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventor: Phillip W. Barth
  • Patent number: 4586242
    Abstract: The organization of a frame portion of an integrated circuit chip to include buffers and drivers as well as a power supply for testing functional elements arranged in a "framed" portion of the chip permits smaller drivers and buffers and a lower power supply to be used during later normal operation. The frame portion may be separated completely after testing.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: May 6, 1986
    Assignee: AT&T Bell Laboratories
    Inventor: Marc L. Harrison
  • Patent number: 4583281
    Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.
    Type: Grant
    Filed: March 13, 1985
    Date of Patent: April 22, 1986
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Manjin J. Kim
  • Patent number: 4581813
    Abstract: A method for fabricating a thermocouple unit for service in and about nuclear reactors and other radioactive environments. The method provides a thermocouple encapsulated within a sphere of fissile material.
    Type: Grant
    Filed: October 17, 1984
    Date of Patent: April 15, 1986
    Assignee: General Electric Company
    Inventor: James H. Terhune
  • Patent number: 4581815
    Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it are disclosed. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon having selected portions thereof reacted with a metal capable of forming a metal silicide in situ on the surface of the poly silicon strips, a further oxide layer over the metal silicide, and a metal layer providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer above the poly load resistor. This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure.
    Type: Grant
    Filed: March 1, 1984
    Date of Patent: April 15, 1986
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robin W. Cheung, Hugo W. K. Chan
  • Patent number: 4581623
    Abstract: A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.
    Type: Grant
    Filed: May 24, 1984
    Date of Patent: April 8, 1986
    Assignee: Motorola, Inc.
    Inventor: Karl L. Wang
  • Patent number: 4580330
    Abstract: An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: April 8, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Gordon P. Pollack, Clarence W. Teng, William R. Hunter, Christopher Slawinski, Robert R. Doering
  • Patent number: 4577394
    Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: March 25, 1986
    Assignee: National Semiconductor Corporation
    Inventor: John L. Peel
  • Patent number: 4577391
    Abstract: A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: March 25, 1986
    Assignee: Monolithic Memories, Inc.
    Inventors: Steve Hsia, Paul Chang
  • Patent number: 4574468
    Abstract: A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.
    Type: Grant
    Filed: October 4, 1984
    Date of Patent: March 11, 1986
    Assignee: U.S. Philips Corporation
    Inventors: Jan W. Slotboom, Henricus G. R. Maas, Johannes A. Appels, Francois M. Klaassen
  • Patent number: 4574466
    Abstract: In a 1.2 micron CMOS process, the gate oxide is formed by growing a 1000 Angstrom thickness of sacrificial oxide, immediately performing an oxide strip and then effecting a thin gate oxidation. The gate oxidation step is characterized by a temperature ramp from 700 to 950 degrees Centigrade in a flow of 9 liters per minute nitrogen and 0.36 liters per minute oxygen. At the 950 degrees Centigrade point, the nitrogen flow ceases and the oxygen flow increases to 9 liters per minute. The temperature is then downwardly ramped to 900 degrees Centigrade.
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: March 11, 1986
    Assignee: GTE Communication Systems Corporation
    Inventors: George F. Hagner, Kothandaraman Ravindhran
  • Patent number: 4574470
    Abstract: A semiconductor chip module with a flat mounting surface is disclosed. A wafer-scale silicon semiconductor chip is provided with electronic circuits formed therein. The chip has a metallized back face and contacts on the opposite, front face. A solder layer secures the metallized back face of the chip to the mounting surface substantially without voids.
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: March 11, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventor: Roy J. Burt
  • Patent number: 4571819
    Abstract: A method for forming trench isolation oxide using doped silicon dioxide which is reflowed at elevated temperatures to collapse any voids therein and produce surface planarity. An underlying layered composite selected from oxide, polysilicon and silicon nitride permits the formation and reflow of the doped isolation oxide and remains in place in the trench to contribute to the trench isolation structure.
    Type: Grant
    Filed: November 1, 1984
    Date of Patent: February 25, 1986
    Assignee: NCR Corporation
    Inventors: Steven H. Rogers, Randall S. Mundt, Denise A. Kaya
  • Patent number: 4571818
    Abstract: A semiconductor structure including a pair of single-crystal semiconductor bulk regions (10.3, 12.2) of differing first and second bulk conductivities, respectively, for forming semiconductor circuits therein, is fabricated whereby each such region is electrically isolated from the other and from a rigid body (20) supporting these regions. The structure is formed by forming at a major surface of a single crystal semiconductor water (10) having the first bulk conductivity a bulk zone (12.1) having the second bulk conductivity, followed by the steps of (1) forming in the wafer (10) at the major surface (10.6) thereof a V-shaped groove (10.2) at the boundary of the bulk zone (12.1) using a crystallographic orientation dependent etch, in order to define the regions (10.3, 12.2) of differing conductivities, (2) forming a dielectric layer (15.1, 15.
    Type: Grant
    Filed: September 29, 1983
    Date of Patent: February 25, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: McDonald Robinson, Harry T. Weston, Yiu H. Wong