Abstract: A thermal oxide is grown on a semiconductor substrate containing single crystal, dielectrically isolated tubs. A silicon nitride layer, serving as a mask for complete self-alignment of collector contacts, bases and emitters is then deposited. After the silicon nitride is patterned, the wafer is reoxidized. The oxide over the emitter and collector contact areas is then etched using the previously patterned silicon nitride film as an alignment mask. The remaining silicon nitride is stripped, a base photoresist pattern is formed and a base impurity ion implant is performed, to define the essential profile of the base. Polysilicon is then deposited and implanted with impurities to form 4000 ohm/square resistors. Silicon dioxide is deposited over the areas of polysilicon which are to become resistors when the polysilicon is patterned, which silicon dioxide masks the polysilicon resistor precursors from the impurities implant conducted for the collector contact, emitter and interconnects.

Abstract: A process for reducing the particle current in the sub-gap range of all-Nb Josephson junctions. The process results in junctions having substantially increased values of V.sub.m. In order to reduce the single particle current, the reaction between the barrier layer oxide and the counter electrode is prevented by additional process steps. After forming the tunnel barrier (4) and before depositing the counter electrode (9), the tunnel barrier surface is covered with a thin, non-continuous layer (5) of a material such as gold which is not reacting with oxygen at process conditions. Subsequently, the non-covered barrier layer surface regions (7) are strongly oxidized thereby forming an oxide layer (8) of sufficient thickness to prevent electron tunneling in these regions.

Abstract: Solid state electronic devices are optically monitored during fabrication to detect hot spots which are indicative of faulty operation. The surface temperatures of such a device are measured by applying a fluorescent material to the device, and subsequently monitoring the temperature dependent fluorescence of the material, which is reflective of the temperature of the underlying device. Devices are accepted, rejected, or further processed in response to the monitored fluorescence.

Abstract: Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.

Abstract: A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.

Abstract: A method for manufacturing a plastic encapsulated semiconductor device is provided which comprises the steps of: clamping by upper and lower molds at least external leads and strips of a semiconductor device assembly formed using a lead frame which has a first connecting band connected to the external leads extending from one side of a substrate support further used as a heat sink, and a second connecting band connected to the strips having portions of small cross-sectional areas and of a predetermined length and extending from the other side of the substrate support, the cross sections being perpendicular to an extending direction of the strips, so that the substrate support may float in a cavity formed by the upper and lower molds and parts of the portions of small cross-sectional areas may be disposed in the cavity and the remaining parts thereof may be disposed between the upper and lower molds; injecting a plastic into the cavity; and cutting the portions of small cross-sectional areas of the strips whic

Abstract: Electronic chip having a composite stratified metal back and method of making it in which strata of metal and/or metal alloys are deposited on the back of the silicon base or a wafer carrying a plurality of circuit components on its face at least one of the strata being resistant to passage of copper at attaching and operational temperatures, and a stratum of solder is provided on the surface of the previously deposited strata for joining the chip to a lead frame.

Abstract: A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

Abstract: A steep-walled mesa is defined by ion beam, plasma or orientation dependent etch, and has a thick insulating layer over its uppermost surface. The material of the mesa is undercut to leave the insulating layer overhanging. Further insulating material is then formed thinly over the exposed mesa material and conductive material deposited giving good coverage of the insulated side-walls of the mesa. Excess conductive material is removed by ion-beam milling, leaving a conductive material gate in the shadow of the cap-like insulating layer.The orientation dependent etchant diazine catalyzed ethylene diaminepyrocatachol-water solution is used to form {111} crystal plane steep side-walled mesa from (110) surface oriented silicon, and aluminium metal conductive material deposited by chemical vapor deposition.

Abstract: A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region.

Abstract: A method of forming on a substrate a layer of silicon-rich metal silicide such as tungsten silicide, WSi.sub.x where x>2 by cosputtering a tungsten disilicide (WSi.sub.2) target and a doped silicon target on to the substrate which is maintained at room temperature. When the silicon-rich silicide is deposited on a doped polysilicon layer the resulting silicon-rich metal silicide/polysilicon sandwich layer has a low resistivity and is suitable for forming therefrom gates and interconnecting conductors for integrated circuit devices.

Abstract: A system for producing electrolyte impregnated capacitor elements comprises a reforming device for reforming the leads of capacitor elements which are brought thereto, a clutch device for clutching the reformed capacitor elements, an aligning device for aligning a predetermined number of the reformed capacitor elements, a holding device holding the aligned capacitor elements, an electrolyte impregnating vessel receiving the aligned capacitor elements to impregnate with the electrolyte, a blow-off device for blowing off the excess amount of electrolyte from the electrolyte impregnating capacitor elements, and transmission devices each operated in a predetermined sequence to transmit the capacitor elements between the above mentioned capacitor element treating devices.

Abstract: A semiconductor device in which a silicon pellet is mounted on a ceramic substrate by means of a glass material of low melting point. To prevent the silicon pellet from being destroyed under thermal stress, the pellet is bonded to the glass material of low melting point through interposition of an adhesion reinforcing film such as an aluminium film capable of exhibiting a good wettability and a great bonding strength.

Abstract: A semiconductor structure is fabricated using a process involving all ion implantation and using only five masks prior to metallization. A buried contact mask is used to form a buried contact layer (114), an isolation mask is used to form grooves (130a, 130b) in an epitaxial layer of silicon (113), a self-aligned transistor mask is used to form a mask (134a to 134e) to define the areas in which emitters (138a, 140b, 140c) bases (113, 139) and contact regions (140a) are to be formed, a base exclusion mask (135a,b) is provided to exclude certain impurities from being implanted into a region to be formed of one conductivity type, and a second exclusion mask (137a, 137b) is provided to exclude impurities to be implanted in a region of opposite conductivity type from the prohibited regions of the structure.

Abstract: In a method for manufacturing a display, a substrate having a surface on which a plurality of light-emitting diodes are aligned is disposed such that the surface opposes a surface of a table. A resin of a light-emitting and electrically insulating material which is kept in a fluid state is filled by capillarity into a space defined by the surface of the substrate and the surface of the table. The resin is then hardened, and the table is removed from a hardened resin. A display is obtained wherein at least the space between the adjacent LEDs is filled with the hardened resin.

Abstract: The rate of oxygen precipitation in a semiconductor wafer during heat treatment is reduced by quickly inserting the wafer into a furnace which has been preheated to the heat treatment temperature. After performing the heat treatment, the wafer is slowly cooled to prevent warpage or cracking.

Abstract: A method of forming a superconductor-barrier-superconductor junction device by the steps of depositing a first superconductive layer on a substrate, forming a barrier layer on the first superconductive layer and depositing a second superconductive layer on the barrier layer. A layer of photoresist is then deposited over the second superconductive layer and patterned together with the second superconductive layer to form a mesa structure. A dielectric layer is deposited over the mesa structure, and the photoresist layer portion is dissolved thereby lifting off the dielectric portion overlying said second superconductive layer portion.

Abstract: Coplanar interdigitated gate and emitter contacts are accessible at the surface of a large area wafer forming a high power, high speed controlled rectifier. A pressure contact is made to the emitter contact which is raised above the level of the gate contact. The upper surface of the gate contact is anodized to provide an insulation layer which prevents accidental shorting of the gate to the emitter contact.

Abstract: A method of making a series connected array of amorphous silicon solar cells on a single substrate includes forming a plurality of spaced conductive lower electrodes on the substrate. Metal electrode stripes are applied on each of the lower electrodes. A layer of amorphous silicon is formed over the lower electrodes, metal electrode stripes and any exposed portions of the surface of the substrate. A plurality of spaced upper conductive electrodes are formed over the amorphous silicon layer with each of the upper electrodes having a portion overlying the electrode stripe on the lower electrode of an adjacent cell. The array is heated to spike the electrode stripes completely through the amorphous silicon layer to contact the overlying upper electrode and thereby electrically connect the cells in series.

Abstract: A structure is provided which affords radiation protection to semiconductor devices and which specifically prevents soft failures in semiconductor memories caused by alpha particle radiation. The protection is provided by a metallic radiation shield formed on but insulated from the semiconductor memory array. The radiation shield is formed on the semiconductor devices while they are still in wafer form but after the normal device fabrication has been completed.