Abstract: A method of manufacturing a semiconductor device wherein a thickness of an insulating film at a peripheral portion of an element formation region of a semiconductor substrate is increased. The feature of this method is that an antioxidant film is formed on the element formation region and subsequently said semiconductor substrate is exposed to an oxygen atmosphere, thereby locally oxidizing that portion of the film which surrounds said element formation region.

Abstract: A method of making a semiconductor device having multi-levels of polycrystalline silicon conductors insulated from each other and from the silicon substrate on which the semiconductor device if formed. In this method, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.

Abstract: Solid electrolytic capacitors are made in a batch process by etching a tantalum foil to form a number of rows of teeth, screen-printing tantalum powder ink onto the teeth, processing the sheet through sintering, anodizing and manganesing stages, sequentially encapsulating opposite edges of the rows of teeth in conductive epoxy and the "gap" with insulating epoxy and separating the individual capacitors from the rows.

Abstract: A semiconductor member is attached to a base by placing a wafer of solder material on the base, placing a carrier member having a through capillary hole on the solder wafer, placing the semiconductor member on the carrier member and heating the arrangement whereby the solder material melts to solder the carrier member to the base, the solder material also travelling via the capillary hole to solder the semiconductor member to the carrier member.

Abstract: At present, the majority of semiconductor devices are two-dimensional large-scale integration (LSI) semiconductor devices in which the semiconductor elements are arranged in a semiconductor layer in a two-dimensional manner. An aim of the techniques of production of semiconductor devices is to achieve, in the future, a super high integration amounting to 16 M bits or more per chip. For attaining such a super high integration, a multilayer semiconductor device must be produced. A method for producing a three-dimensional LSI semiconductor device prevents wasteful formation of semiconductor layers and insulating films. The method includes the step of forming, in a first semiconductor layer, a monitoring device for evaluating the circuit function of the semiconductor elements in the first semiconductor layer and subsequently forming another semiconductor layer above the first semiconductor layer.

Abstract: A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

Abstract: A method for diffusing a conductively determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a layer of a rare earth boride material over a predetermined surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the boride material to diffuse into the adjoining portion of the substrate to modify its conductive characteristics. At the same time a good electrical ohmic contact is established between the boride material and the adjoining substrate portion while the boride material retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.

Abstract: In manufacture of VLSI semiconductor devices, the insulator surface upon which a metallization pattern is deposited must be smooth to facilitate lithographic operations. This requires the insulator to be thick and flowed or otherwise treated to eliminate steep edges. A contact hole etched in a thick insulator has steep sidewalls, however, and so chemical vapor deposition is preferrably used for the metallization so the sidewalls will be coated. A thin insulator coating is deposited after the contact holes are etched and prior to metallization to cover the low-resistance flowed insulator and self-align the contacts.

Abstract: Contacts between polysilicon conductors on the surface of a silicon wafer and doped regions underlying them in the wafer, rendered defective by the growth of a thin intervening oxide layer between conductors and diffusions, are repaired by depositing dots of aluminum on the conductors in the contact areas and annealing the wafer so as to drive traces of the aluminum through the conductors and the intervening oxide into the underlying doped regions in the wafer.

Abstract: The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

Abstract: A method of forming a high-low junction emitter silicon solar cell including the producing of an electron accumulation layer by oxide-charge-induction.

Abstract: A method for manufacturing a solid electrolyte condenser encapsulated with an insulating resin, wherein a solder layer is partially formed on a cathode current collecting layer to be connected with a cathode terminal and the solder layer is subsequently remelted and solidified while contacted by the cathode terminal 5 to connect the cathode terminal 5 for the purpose of avoiding any possible spattering of solder of the solder layer connecting the cathode terminal to the cathode current collecting layer, any breakage or any defect in appearance.

Abstract: A process for fabricating doped regions in a semiconductor substrate 10 beneath regions of oxidized silicon 21 includes the steps of fabricating a first mask 23 over the substrate 10 except where field regions 21 are desired, introducing p type impurity 30 in to the unmasked regions, oxidizing the silicon substrate 10 except where overlayed by the first mask 23 to form field regions 21, fabricating a second mask 28/23 over the semiconductor substrate 10 except for second field regions, introducing n conductivity type impurity 32 into the second field regions, and oxidizing the substrate to form second field regions 21.

Abstract: An annealing method wherein an elongated irradiation area is formed by a light source whose emitted light is controlled so that a peak curve of the illuminance distribution in the area may be substantially linear and that equiluminous curves near the peak curve may be substantially parallel therewith. A semiconductor wafer and the irradiation area are moved relative to each other in such a manner that the entire area of the semiconductor wafer to be annealed may cross all the equiluminous curves, thereby to achieving the annealing of the semiconductor wafer. With this annealing method, semiconductor crystals are satisfactorily recovered from damages incidental to ion implantation into the semiconductor wafer and polycrystalline or amorphous semiconductors are converted into single crystal semiconductors of good quality.

Abstract: A method for diffusing a conductivity determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a conductive layer made of a rare earth hexaboride material containing a predetermined amount of silicon in it over a surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the hexaboride material to diffuse into the adjoining portion of the substrate to modify its conductor characteristics. At the same time a good electrical ohmic contact is established between the conductive layer and the adjoining substrate portion while the conductive layer retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.

Abstract: A high resistance semiconductor substrate body with a thin low resistance active semiconductor layer thereon is generated by a method including the steps of subjecting the semiconductor substrate body to neutron bombardment to a degree which produces high resistance in the semiconductor body and whereby doping substances are generated in the substrate body by the thermal neutron bombardment. A thin low resistant active semiconductor layer is then generated on the substrate body by annealing, a surface of the semiconductor substrate body up to a selected depth by laser radiation or electron radiation such that the lattice deterioration which was caused by the neutron bombardment is eliminated but the doping which was generated by the transmutation of elements during neutron bombardment remains. The annealing can be undertaken only in selected regions on the surface of the semiconductor substrate body, thereby facilitating the construction of integrated circuit components thereon.

Abstract: The substrate of a gallium nitride light-emitting diode is made rough at given positions on the surface thereof, or an insulating film strip pattern is attached on the surface of the substrate prior to growing an n-type conductive gallium nitride layer and a semi-insulating gallium nitride layer thereon. As a result, high conductivity regions are formed in the semi-insulating layer at positions corresponding to the rough surfaces or the insulating film strip pattern in such a manner that each of the high conductivity region extends from the n-type conductive layer to the upper surface of the semi-insulating layer so as to function as a conductor to be connected to an electrode. In the same manner similar high conductive regions are made along kerf portions in a diode wafer, preventing each diode chip from being damaged on cutting.

Abstract: A method for making a thin-film transistor wherein a gate insulating layer is formed by anodizing two oxide layers on the substrate and then etching the assembly to completely remove the uppermost one of these layers to leave the lowermost layer so as to serve as the gate insulating layer.

Abstract: In semiconductor devices, the transistors are isolated by means of either a PN junction isolation method or a passive isolation (PI) method. The present invention aims to improve the PI method, which is disadvantageous in that an electrode, electrically connected to the semiconductor substrate, causes a decrease in the integration density of the IC chip. In the present invention, the vacant space outside the element-forming regions is used to form the electrode and the integration density is not decreased due to the formation of the electrode. Since a polycrystalline silicon layer is in a groove formed in the vacant space, ohmic contact between the polycrystalline semiconductor material in the layer and the semiconductor substrate can be achieved while at the same time keeping the diffusion length of the impurities diffused from the polycrystalline silicon layer and the semiconductor substrate, very short. Therefore, upward diffusion of the impurities from the N.sup.

Abstract: Method of manufacturing a semiconductive device which comprises: positioning plural semiconductive chips on a film so that one surfaces of the chips form a flat plane; connecting the semiconductive chips with insulative member to make one conjoined body; thereafter removing the film from the conjoined body; securing the conjoined body on a wiring board and forming metallic wires which connect the wiring board and the semiconductive chips in a manner that the wires be closely fit to the flat plane of the conjoined body.