Abstract: In one embodiment, an apparatus comprises an input power interface for receiving input power, a power control system for transmitting DC (Direct Current) pulse power on multiple phases over a cable to a plurality of powered devices and verifying cable operation during an off-time of pulses in the DC pulse power, and a cable interface for delivery of the DC pulse power on the multiple phases and data over the cable to the powered devices. A method for transmitting multiple phase pulse power is also disclosed herein.

Abstract: A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

Abstract: A method comprises analyzing performance data of a system using one or more machine learning techniques. The system comprises a plurality of hardware components. In the method, a priority list of the plurality of hardware components is generated based on the analysis, and power from one or more power sources is distributed to one or more of the plurality of hardware components based on the priority list.

Abstract: A power/data transmission breakout system includes a power/data transmission breakout device coupled to a powering device and each of a plurality of powered devices. The power/data transmission breakout device receives power and data from the powering device via a first power/data cable that is connected to the power/data transmission breakout device, and identifies a first powered device as a destination for the data. The power/data transmission breakout device then transmits a respective subset of the power that was received from the powering device via each of a plurality of second power/data cables that are each connected to the power/data transmission breakout device and a respective one of the plurality of powered devices, and transmits the data along with the respective subset of the power that was received from the powering device via the second power/data cable that is connected to that first powered device.

Abstract: A hypervisor receives a notification from a guest operating system (OS) of a virtual machine (VM), where the notification indicates a guest OS access of a memory address associated with a device slot of a communication bus, where the device slot is unavailable to the guest OS; maps, in a page table of the hypervisor, a page table entry for a memory configuration space of the device slot to the memory address, where the page table entry indicates that the configuration space is available to the guest OS; identifies an additional device slot associated with the communication bus; and maps, in the page table, an additional page table entry for an additional memory configuration space of the additional device slot to an additional memory address, where the additional page table entry indicates that the additional configuration space is available to the guest OS.

Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Abstract: Mobile devices, such as smartphones, are severely battery-limited. The capabilities of mobile device processors have increased at exponential rates, but battery technologies have improved at much slower rates. As a consequence, it is ever more important that mobile devices be operated in battery-preserving manners. An aspect of the present technology concerns methods and arrangements enabling on-going recognition-processing of imagery and audio by different detectors, without the high battery drain that has characterized the prior art. A variety of other features and arrangements are also detailed.

Abstract: Examples herein disclose monitoring an expected functionality upon execution of a system management mode (SMM) code. The examples detect whether a change has occurred to the SMM code based on the monitoring of the expected functionality. The change indicates that the SMM code is compromised.

Abstract: Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

Abstract: Methods, Apparatus, and Systems are discussed for a sequencer-based protocol adapter that executes a limited instruction set. The sequencer-based protocol adapter is implemented in electronic hardware and programmable registers in an integrated circuit and configured to transition a set of 1) one or more voltage sources, 2) one or more frequency sources, or 3) a combination of voltage sources and frequency sources, coupled with that sequencer-based protocol adapter. The sequencer-based protocol adapter manages power on the integrated circuit, via receiving a desired performance index at an input and then executing one or more of the limited instructions stored in the programmable registers in a proper sequence of steps in order to transition the coupled voltage sources and/or frequency sources from a current operational state to a desired operational state. Note, the desired operational state the coupled voltage sources and/or frequency sources corresponds to the received desired performance index.

Abstract: A computing system includes a system board having a system controller device with an interrupt input. A system expansion bus connector is located on the system board and includes power pin(s) and an interrupt signal pin connected to the interrupt input. A peripheral device expansion card system is coupled to the computing system through system expansion bus connector and includes a system power reporting device coupled to the power pin(s) to receive power from the computing system via the power pin(s), and a card controller device coupled to the system power reporting device and to the interrupt signal pin. The card controller device determines, using the system power reporting device, a power state of the computing system. The card controller device also sends, to the system controller device through the interrupt signal pin, an interrupt signal that the system controller device interprets as a hot plug event.

Abstract: A method for saving and/or restoring settings of an instrument for processing a sample or reagent is disclosed. The instrument comprises a control unit and an operating system. A storage medium is provided to the instrument. The storage medium comprises a script. The script restores data for restoring settings of the instrument. The script is encrypted and/or digitally signed. The method verifies an identity and/or integrity of the script and executes the script upon starting the instrument by the operating system with the storage medium when the identity and/or integrity of the script correspond to an identity and/or integrity of the instrument. The control unit provides an input menu for allowing a user to input a saving and/or restoring command. The instrument saves settings on the storage medium and/or restores settings of the instrument from the storage medium by the restoring data corresponding to the saving and/or restoring command.

Abstract: A background process is configured to periodically scrub a boot storage of a storage controller to ensure operational correctness of the boot storage. One or more foreground processes store a system configuration data of the storage controller in the boot storage of the storage controller. The background process and the one or more foreground processes are executed to meet predetermined performance requirements for the background process and the one or more foreground processes.

Abstract: An example power module includes an energy storage device, an energy storage carrier, and an electrical connector. The energy storage carrier houses the energy storage device and is removably insertable into a modular data storage slot of a computing device. The modular data storage slot has a data path and a first power path to removably couple to a data storage module. The electrical connector is to transfer energy from the energy storage device to a second power path associated with the modular data storage slot.

Abstract: Disclosed are devices, systems, and methods for the use of memory including a data table configured to store a plurality of elements, wherein the plurality of elements are arranged into a plurality of buckets and each of the plurality of buckets comprising a plurality of entries. A first power domain can be associated with an entry of each bucket or with a first bucket. A second power domain can be associated with a second entry of each bucket or a second bucket. Processing logic can be configured to search for a particular value stored in an element of the plurality of elements by selecting buckets of the plurality of buckets and selecting at least one entry of each of the buckets. A programmable register can be used to select a powered state of the second power domain based on a configuration of the programmable register.

Abstract: A method for booting a computer system includes: loading a first stage bootloader of a plurality of first stage bootloaders from a boot image based on a known configuration of the computer system; executing the first stage bootloader to identify a selected bootbank of a plurality of bootbanks in the boot image based on the known configuration of the computer system; executing, by the first stage bootloader, a second stage bootloader from the boot image with an instruction to boot from the selected bootbank; and executing, by the second stage bootloader, a binary file in the selected bootbank.

Abstract: An integrated computing system configuration system includes a computer-based system that when executed, receives component definitions associated with physical components that are to be configured in a portion of a first sub-system of a first customized integrated computing system. Using the received component definitions, the system generates the first sub-system definition, which can be combined with a second sub-system definition to form a first integrated computing system. The system may also combine the first sub-system definition with another second sub-system definitions to form a second customized integrated computing system definition that is different from the first customized integrated computing system definition.

Abstract: Techniques are provided for managing power delivery to multiple universal serial bus (USB) type-C ports of a desktop computer system. In an example, a method can include providing a first power level to a USB power delivery controller during a non-sleep mode operation of the desktop computer, and providing a second power level to the USB power delivery controller when the computer is in a sleep mode, the second power level configured to provide default charge power to a connected device when the computer is in the sleep mode.

Abstract: Examples provide for automatically provisioning hosts in a cloud environment. A cloud daemon generates a cloud host-state configuration, for a given cloud instance of a host, stored on a cloud metadata service prior to first boot of the given cloud instance of the host. A first boot of a plurality of cloud instances of hosts is performed using a stateless, master boot image lacking host-specific configuration data. On completion of the first boot of a given cloud instance of a host, the cloud host-state configuration is installed on the master boot image to generate a self-configured boot image including host-specific configuration data for the given cloud instance of the host. A second boot is performed on the given cloud instance of the host by executing the self-configured boot image to automatically provision the given cloud instance of the host in the cloud environment.