Patents Examined by Albert Wang
  • Patent number: 10444821
    Abstract: A power supply control unit in a power supply unit in a multi-functional peripheral turns off a PFC unit in a power-saving mode. If a return to a normal mode occurs, whether the PFC unit is to be turned on or not is controlled based on a cause of the return to the normal mode. If the PFC unit is not to be turned on or already has an ON state based on the occurrence of the return, the power supply control unit immediately causes power supply unit to start power supply based on the cause of return. If the PFC unit is turned on based on the occurrence of the return, the power supply control unit causes the power supply unit to start power supply based on the cause of return after a lapse of a delay time from the turning on of the PFC unit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 15, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuhiro Kozuka
  • Patent number: 10417030
    Abstract: An apparatus and method for reducing boot time of an electronic device are provided. The electronic device includes electronic device is provided. The electronic device includes a processor including at least one system register; and an Operating System (OS) including an OS component having at least one reserved area, each reserved area including a static memory structure. The OS component is configured to, during a booting process, copy addresses of the at least one static memory structure into at least one of the plurality of system registers, and initialize the static memory structures located at the copied addresses.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kirk R Swidowski, Ahmed M Azab
  • Patent number: 10417427
    Abstract: A first firmware volume of a Unified Extensible Firmware Interface (UEFI) compliant information handling system is accessed. Authentication information is retrieved from the first firmware volume using a UEFI Secure Architecture Protocol. Based on the authentication information, it is determined if the first firmware volume is a first type of firmware volume. If the first firmware volume is the first type of firmware volume, the first firmware volume is authenticated using the first authentication information and an authentication procedure other than Secure Boot authentication. If the first firmware volume is a second type of firmware volume, the second type different than the first type, the first firmware volume is authenticated using the first authentication information and the Secure Boot authentication.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 17, 2019
    Assignee: Dell Products, LP
    Inventors: Yogesh P. Kulkarni, Sundar Dasar, Sumanth Vidyadhara
  • Patent number: 10417013
    Abstract: An integrated computing system configuration system includes a computer-based system that when executed, receives component definitions associated with physical components that are to be configured in a portion of a first sub-system of a first customized integrated computing system. Using the received component definitions, the system generates the first sub-system definition, which can be combined with a second sub-system definition to form a first integrated computing system. The system may also combine the first sub-system definition with another second sub-system definitions to form a second customized integrated computing system definition that is different from the first customized integrated computing system definition.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 17, 2019
    Assignee: VCE IP Holding Company LLC
    Inventors: Kenneth R. Anderson, Mark S. Tuck, Daniel J. Butzer, Collin J. Miller, Darrell J. Dillon
  • Patent number: 10416705
    Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Hyeong Soo Jeong
  • Patent number: 10409351
    Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 10, 2019
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Bernhard Egger, Younghyun Cho, Su-Rim Oh, Dong-hoon Yoo
  • Patent number: 10401940
    Abstract: For power management in a disaggregated computing system, a set of initial electrical power levels are allocated to a set of processor cores according to a predicted desired workload, where the set of initial power levels aggregate to an initial collective contracted power level. Electrical power is dynamically allocated to respective processor cores within the set of processor cores to produce a capacity to execute a collective demanded workload while maintaining the electrical power to the set of processor cores to an approximately constant electrical power level within a threshold of the initial collective contracted electrical power level.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruchi Mahindru, John A. Bivens, Koushik K. Das, Min Li, HariGovind V. Ramasamy, Yaoping Ruan, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10387651
    Abstract: Examples herein disclose monitoring an expected functionality upon execution of a system management mode (SMM) BIOS code. The examples detect whether a change has occurred to the SMM BIOS code based on the monitoring of the expected functionality. The change indicates that the SMM BIOS code is compromised.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: August 20, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey Kevin Jeansonne, Boris Balacheff, Valiuddin Ali, Chris I Dalton, David Plaquin
  • Patent number: 10387187
    Abstract: A method of rebooting a computing system in which a virtual machine (VM) runs on top of a hypervisor and a host operating system (OS) includes the following steps. Those steps are sending, from the host OS to the hypervisor, a pre-reboot notification that the host OS is going to reboot, in response to reception of the pre-reboot notification, saving by the hypervisor state of a session that is executing in the VM, rebooting the host OS, after the host OS is rebooted, logging on to the host OS using a credential provider that was previously registered with the host OS and sending a post-reboot notification from the host OS to the hypervisor, and in response to reception of the post-reboot notification, instantiating by the hypervisor a VM in which the session is resumed using the saved state of the session.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 20, 2019
    Assignee: VMware, Inc.
    Inventors: Zhikai Chen, Zhibin He, Xi Chen, Wen Wang
  • Patent number: 10386903
    Abstract: A method for migrating a power shelf between being supplied single-phase power and three-phase power includes coupling a second power adapter to an input of a power shelf of a rack while power is being supplied to the power shelf via a first power adapter coupled to another input of the power shelf. The first power adapter includes a multi-pin connector coupled to the input and three other connectors each coupled to respective single-phase power sources and the second power adapter includes a multi-pin connector configured to couple with the other input and another connector configured to couple with a three-phase power source.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 20, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Jon Moen, Brandyn David Giroux, Jing Wang
  • Patent number: 10379870
    Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 13, 2019
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Alexander Fainkichen, Ye Li
  • Patent number: 10379943
    Abstract: A background process is configured to periodically scrub a boot storage of a storage controller to ensure operational correctness of the boot storage. One or more foreground processes store a system configuration data of the storage controller in the boot storage of the storage controller. The background process and the one or more foreground processes are executed to meet predetermined performance requirements for the background process and the one or more foreground processes.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen, Karl A. Nielsen
  • Patent number: 10365708
    Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Simon N. Peffers, Sean M. Gulley, Thomas L. Dmukauskas, Aaron Gorius, Vinodh Gopal
  • Patent number: 10346177
    Abstract: An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Mahesh S. Natu, Wei Chen, Jing Ling, James E. McCormick, Jr.
  • Patent number: 10331187
    Abstract: Systems and methods are provided to selectively provide power to a power supply line in a connector port. A power setting may be received, at a controller in an electronic device, for the connector port. The power setting may be set or changed by a processor in the electronic device. The power setting may be stored in a non-volatile storage. The controller may determine the power setting by reading the non-volatile storage. The controller may then apply the power setting to a switch using at least one control signal. The control signal selectively opens and closes the switch to respectively connect and disconnect a source of DC power to the power supply line in the connector port.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventor: Kamal Lee
  • Patent number: 10318468
    Abstract: An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: June 11, 2019
    Assignee: STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING CO., LTD.
    Inventors: Jian Zhang, Qunxing Jiang, Xiaokai Wang
  • Patent number: 10317973
    Abstract: A computing system includes a system board having a system controller device with an interrupt input. A system expansion bus connector is located on the system board and includes power pin(s) and an interrupt signal pin connected to the interrupt input. A peripheral device expansion card system is coupled to the computing system through system expansion bus connector and includes a system power reporting device coupled to the power pin(s) to receive power from the computing system via the power pin(s), and a card controller device coupled to the system power reporting device and to the interrupt signal pin. The card controller device determines, using the system power reporting device, a power state of the computing system. The card controller device also sends, to the system controller device through the interrupt signal pin, an interrupt signal that the system controller device interprets as a hot plug event.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 11, 2019
    Assignee: Dell Products L.P.
    Inventors: Yimin Xiao, Terry L. Matula
  • Patent number: 10310579
    Abstract: A semiconductor integrated circuit capable of efficiently suppressing power consumption when a power supply voltage is lowered is provided.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 4, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Suguru Kawasoe
  • Patent number: 10310593
    Abstract: The invention relates to an electronic mobile device (10; 20) comprising a device mode control unit (5) arranged to switch the mobile device from a first operational mode into a second operational mode. An orientation sensor (18; 28) is configured to measure a current orientation of the mobile device. A processor (6) periodically receives the current orientation from the orientation sensor, periodically stores the received current orientation as a reference orientation, and periodically calculates a differential angle between the current orientation and the stored reference orientation. The device is switched from the first operational mode to the second operational mode if the differential angle is above a predefined angular threshold value.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 4, 2019
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventor: Harm Kingma
  • Patent number: 10296069
    Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 21, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Stewart, Dexter Chun