Abstract: Anti-fault injection systems and methods are disclosed. An anti-fault injection system includes a processor; a boot ROM configured to store a series of boot instructions executable by the processor; and anti-fault injection controller circuitry. The anti-fault injection controller circuitry is accessible to the processor while the processor is executing the boot instructions. The anti-fault injection controller circuitry includes interrupt/reset circuitry configured to interrupt the processor in response to a trigger and secure boot circuitry. The secure boot circuitry is configured to, in response to being accessed by the processor: determine whether the processor is executing non-secure boot instructions in error; and in response to detecting that the processor is executing non-secure boot instructions in error, provide the trigger to the interrupt/reset circuitry.

Abstract: The application provides a temperature increasing device and a temperature increasing method. The temperature increasing device is arranged on a motherboard including at least one system element. The temperature increasing device includes a power supply module and a controller After the power supply module is triggered, the power supply module outputs an enable signal to the system element and the controller, the controller detects whether the system element operates according to a preset power-on action, if the controller determines that the system element does not operate according to the preset power-on action, the controller outputs an electric signal to enable the temperature of the system element to increase, and when the temperature of the system element is increased to an extent that the controller determines that the system element is capable of operating according to the preset power-on action, the controller stops outputting the electric signal.

Abstract: A power supply circuit includes a first power supply line that couples a first input node from which first input power is input and an output node to each other, a second power supply line that couples a second input node from which second input power is input and the output node to each other, a power limit of the second input power being higher than that of the first input power, a converter that is inserted in the first power supply line and that converts a voltage of the first input power input from the first input node to a higher voltage or a lower voltage, an adjustment circuit that adjusts an output voltage of the converter to a voltage higher than a voltage of the second input power input from the second input node.

Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.

Abstract: Power control for computer systems with multiple power supplies including receiving a first measurement of power supplied to a computer system by a first power supply; receiving a second measurement of power supplied to the computer system by a second power supply; calculating a total power supplied to the computer system by combining the first measurement of power supplied to the computer system by the first power supply and the second measurement of power supplied to the computer system by the second power supply; comparing the total power supplied to the computer system to a power threshold of the computer system; and in response to determining that the total power supplied exceeds the power threshold of the computer system, shutting off the first power supply.

Abstract: The disclosed technology is generally directed to virtual machines. In one example of the technology, generic virtual machine artifacts are created. The generic virtual machine artifacts include at least one generic compute artifact and at least one generic network artifact. A first virtual machine is composed and booted with the generic virtual machine artifacts. The first virtual machine is caused to enter a state in which the first virtual machine is polling for a configuration with user-specific compute settings, user-specific networking settings, and user-specific storage settings.

Abstract: Systems and methods for providing a tamper-proof, dual-boot Information Handling System (IHS) having Operating System (OS)-specific hardware and/or firmware components. In some embodiments, a method may include: producing, by an Embedded Controller (EC) of an IHS, a Real-Time Clock (RTC) battery-powered General-Purpose Input/Output (GPIO) control or external latch; applying the RTC battery-powered GPIO control to a chip select circuit; and selecting, via the chip select circuit: (i) a first flash memory configured to boot the IHS into a diagnostic mode or first OS, or (ii) a second flash memory configured to boot the IHS into a native OS.

Abstract: A network apparatus (1) including —a base station (10) having a first interface (12); —a docking station (20) connectable with the base station (10) and having a second interface (22); and —at least one transmission module of a plurality of interchangeable transmission modules (13a, 13b) configured to be connected to the base station (10) or to the docking station (20), wherein the transmission modules (13a, 13b) have network interfaces compatible with both the first interface (12) and the second interface (22).

Abstract: Various exemplary embodiments of the present disclosure relate to an apparatus and method for outputting content in an electronic device. In this case, the electronic device includes a display module, a power module configured to interrupt power supply to at least one element of the electronic device based on a control signal, and a processor. The processor may be configured to transmit to the power module the control signal for interrupting the power supply to the processor if a designated condition is satisfied, and transmit content information to the display module so that the display module displays the content information when the power supply to the processor is interrupted.

Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.

Abstract: In one embodiment, a method includes detecting a slave device at a master device, determining at the master device if the slave device is configured for I2C (Inter-Integrated Circuit) or SPE (Single Pair Ethernet) based on an output at the slave device, and selecting an I2C mode of operation at the master device if the slave device is configured for I2C, or selecting an SPE mode of operation at the master device if the slave device is configured for SPE. Data and control are selected from an I2C controller at the master device in the I2C mode of operation and selected from a physical coding sublayer at the master device in the SPE mode of operation.

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Abstract: An image forming apparatus includes a hardware processor including CPUs each including cores, a process being executed by the CPUs, wherein the hardware processor managing the cores causes a first process or a second process to be executed, when the first process is executed, while electric power is uniformly supplied to the cores, allocates a pre-process in which sequential processing is performed to a part of the cores and a post-process in which parallel processing is performed to another part of cores, and when the second process is executed, for a part of the CPUs, allocates the pre-process to a part of the cores while electric power is supplied thereto and causes electric power supply to another part of cores to be stopped, and for another part of the CPUs, allocates the post-process to at least a part of the cores while electric power is uniformly supplied to the cores.

Abstract: Systems and methods for reconfiguration of illumination products are presented. An illumination product comprises components that implement a device access framework to facilitate access to the configuration of the illumination product by external components. Components internal to or otherwise associated with the illumination product codify various configuration parameters associated with the illumination product in one or more files (e.g., text files) and/or file attributes (e.g., filenames). One or more external components coupled to the internal components use a file access API to read from, write to, and/or otherwise manipulate the files (e.g., modify file content and/or file attributes) so as to access and/or affect the configuration parameters. Changes to the configuration parameters invoked by the external components are detected by the internal components and applied to the configuration (e.g., operational settings) of the illumination product.

Abstract: Techniques for providing and maintaining protection of firmware routines that form part of a chain of trust through successive processing environments. An apparatus may include a first processor component (550); a volatile storage (562) coupled to the first processor component; an enclave component to, in a pre-OS operating environment, generate a secure enclave within a portion of the volatile storage to restrict access to a secured firmware loaded into the secure enclave; a first firmware driver (646) to, in the pre-OS operating environment, provide a first API to enable unsecured firmware to call a support routine of the secured firmware from outside the secure enclave; and a second firmware driver (647) to, in an OS operating environment that replaces the pre-OS operating environment, provide a second API to enable an OS of the OS operating environment to call the support routine from outside the secure enclave.

Abstract: An example system includes a server including a power supply and a microcontroller. The power supply may store parameters for a plurality of different ranges of overcurrent and a plurality of corresponding different time periods. The power supply may also receive information from the electrical component corresponding to the speed at which the electrical component can reduce the amount of power the electrical component is consuming. The controller may receive information from the power supply to determine the amount of current that will cause an overcurrent event in the electrical component. The controller may signal the electrical component to reduce the amount of power the electrical component is drawing from the power supply in response to the detected amount of current corresponding to the overcurrent event.

Abstract: The versatility of a power feeding device is improved. A power storage system includes a power storage device and a power feeding device. The power storage device includes data for identifying the power storage device. The power storage device includes a power storage unit, a switch that controls whether power from the power feeding device is supplied to the power storage unit, and a control circuit having a function of controlling a conduction state of the switch in accordance with a control signal input from the power feeding device. The power feeding device includes a signal generation circuit having a function of identifying the power storage device by the data input from the power storage device, generating the control signal corresponding to the identified power storage device, and outputting the generated control signal to the power storage device.

Abstract: In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.

Abstract: A controller of a storage device is described for handling communications with a host device. In some examples, the storage device includes a wide port comprising a plurality of phys. The wide port is configured to receive, via a first phy of the plurality of phys, a signal. The controller is configured to select, based on a respective power factor associated with each respective phy of the plurality of phys and a respective performance factor associated with each respective phy of the plurality of phys, a second phy of the plurality of phys to utilize for performing an operation associated with the received signal. In such examples, the wide port is further configured to perform, using the second phy, the operation associated with the received signal.