Patents Examined by Alexander Belousov
  • Patent number: 10741510
    Abstract: A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least a portion of the semiconductor chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip, wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof and filled with an insulating material.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun Kim, Ji Hye Shim, Seung Hun Chae
  • Patent number: 10741398
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia Nouri, Stefan Landis, Nicolas Posseme
  • Patent number: 10734550
    Abstract: Disclosed herein is a semiconductor device including: a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulating layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer through a first hole of the first insulating layer; a second electrode disposed on the second conductive semiconductor layer through a second hole of the first insulating layer; a first cover electrode disposed on the first electrode; and a second cover electrode disposed on the second electrode, wherein the second cover electrode includes a plurality of pads, and a connecting portion configured to connect the plurality of pads, a width of the connecting portion is smallest at a central position between the adjacent pads, and an area ratio between the second cover electrode and the
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Youn Joon Sung, Rak Jun Choi
  • Patent number: 10734332
    Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Bradley Lasiter, Ravindra Vaman Shenoy, Donald William Kidwell, Jr., Mohammad Ali Tassoudji, Vladimir Aparin, Seong Heon Jeong, Jeremy Dunworth, Alireza Mohammadian, Mario Francisco Velez, Chin-Kwan Kim
  • Patent number: 10732046
    Abstract: A system and method for thermally calibrating semiconductor process chambers is disclosed. In various embodiments, a first non-contact temperature sensor can be calibrated to obtain a first reading with the semiconductor process chamber. The first reading can be representative of a first temperature at a first location. The first non-contact temperature sensor can be used to obtain a second reading representative of a second temperature of an external thermal radiation source. The second temperature of the external thermal radiation source can be adjusted to a first temperature setting of the external radiation source such that the second reading substantially matches the first reading. Additional non-contact temperature sensor(s) can be directed at the external thermal radiation source and can be adjusted such that the reading(s) of the additional non-contact sensors are calibrated and matched to one another.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 4, 2020
    Assignee: ASM IP HOLDING BV
    Inventors: Yen Lin Leow, Caleb Koy Miskin, Hyeongeu Kim
  • Patent number: 10707135
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Hao Tseng, Chien-Ting Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
  • Patent number: 10707375
    Abstract: An embodiment provides a light emitting element comprising: a first conductive semiconductor layer including a first layer and a second layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; and a first electrode and a second electrode arranged on the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, wherein the first layer includes a plurality of first grooves, and a growth prevention layer is arranged on the bottom surface and side surfaces of each of the first grooves.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: July 7, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Youn Joon Sung
  • Patent number: 10693059
    Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Kisup Chung, Injo Ok, Seyoung Kim, Choonghyun Lee
  • Patent number: 10692985
    Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas J. Loubet, Sanjay C. Mehta, Vijay Narayanan, Muthumanickam Sankarapandian
  • Patent number: 10672640
    Abstract: A semiconductor processing apparatus according to the present embodiment is provided with a stage capable of placing a semiconductor substrate thereon and of rotating the semiconductor substrate. A plurality of holders are provided on the stage, to hold an edge of the semiconductor substrate. A plurality of sensors are provided to the plurality of holders, respectively, to detect the edge of the semiconductor substrate. An elevator mechanism is capable of changing heights of the holders. A controller controls the elevator mechanism to change the heights of the holders so that the plurality of sensors detect the edge of the semiconductor substrate.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Junichi Igarashi
  • Patent number: 10658468
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • Patent number: 10651080
    Abstract: Thin AlN films are oxidatively treated in a plasma to form AlO and AlON films without causing damage to underlying layers of a partially fabricated semiconductor device (e.g., to underlying metal and/or dielectric layers). The resulting AlO and AlON films are characterized by improved leakage current compared to the AlN film and are suitable for use as etch stop layers. The oxidative treatment involves contacting the substrate having an exposed AlN layer with a plasma formed in a process gas comprising an oxygen-containing gas and a hydrogen-containing gas. In some implementations oxidative treatment is performed with a plasma formed in a process gas including CO2 as an oxygen-containing gas, H2 as a hydrogen-containing gas, and further including a diluent gas. The use of a hydrogen-containing gas in the plasma eliminates the oxidative damage to the underlying layers.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 12, 2020
    Assignee: Lam Research Corporation
    Inventors: Meliha Gozde Rainville, Nagraj Shankar, Daniel Damjanovic, Kapu Sirish Reddy
  • Patent number: 10651091
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10644192
    Abstract: A method of manufacturing a light-emitting device includes measuring a light distribution of a light-emitting element, sealing the measured light-emitting element by a sealing material including a phosphor, and curing the sealing material by heat treatment. An emission angle dependence of emission chromaticity of the light-emitting device is controlled by setting a degree of settling of the phosphor in the sealing material according to the measured light distribution of the light-emitting element.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 5, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Koji Fukagawa, Takashi Terayama
  • Patent number: 10593836
    Abstract: The light-emitting device according to one embodiment includes a substrate; a plurality of light-emitting cells disposed on the substrate so as to be spaced apart from each other; and a connection line configured to electrically interconnect neighboring light-emitting cells, wherein each of the light-emitting cells includes: a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer disposed on the substrate; and first and second electrodes configured to be electrically connected to the first and second semiconductor layers respectively, wherein the light-emitting cells include: a first power cell configured to receive first power via the first electrode; and a second power cell configured to receive second power via the second electrode, and wherein the first electrode in the first power cell has a first planar shape different from a second planar shape of the second electrode in the second power cell.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: March 17, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Ji Hyung Moon
  • Patent number: 10573728
    Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10566196
    Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 18, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Osamu Ishikawa, Kenji Meguro, Taishi Wakabayashi, Hiroyuki Oonishi
  • Patent number: 10566378
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Patent number: 10559493
    Abstract: A method for semiconductor device fabrication includes forming storage elements on conductive structures. A cap layer is deposited over the storage elements and the conductive structures. An interlevel dielectric (ILD) layer is formed over the cap layer. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed to expose the conductive structures therebelow to form via openings. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe