Patents Examined by Alexander Belousov
  • Patent number: 11069702
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyasu Sato
  • Patent number: 11069523
    Abstract: A method and apparatus for material deposition onto a sample to form a protective layer composed of at least two materials that have been formulated and arranged according to the material properties of the sample.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 20, 2021
    Assignee: FEI Company
    Inventors: Brian Roberts Routh, Jr., Thomas G. Miller, Chad Rue, Noel Thomas Franco
  • Patent number: 11056568
    Abstract: A method is provided. First and second fins are etched to form a first recess over the etched first fin and a second recess over the etched second fin. A first composite fin and a second composite fin are concurrently epitaxially grown respectively in the first recess and the second recess. The first composite fin includes a plurality of nanowire channels and at least one sacrificial layer. The second composite fin includes at least one nanowire channel and at least one sacrificial layer. A number of the plurality of nanowire channels of the first composite fin is greater than a number of the at least one nanowire channel of the second composite fin. A dielectric material is recessed to expose at least a portion of the first composite fin and at least a portion of the second composite fin.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Georgios Vellianitis, Gerben Doornbos
  • Patent number: 11024544
    Abstract: Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 1, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Lamine Benaissa, Laurent Brunet
  • Patent number: 11018151
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, the memory films containing a charge storage layer and blocking dielectric which generally extend along the first horizontal direction and laterally undulate along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 25, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Ryosuke Kaneko
  • Patent number: 11011635
    Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 18, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sheng-Chin Kung, Hua Chung
  • Patent number: 11011698
    Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
  • Patent number: 11004698
    Abstract: Provided is a power module package including: a substrate; at least one electrode arranged on the substrate; and an encapsulation member covering at least a portion of the substrate, the encapsulation member including a housing unit housing the at least one electrode. The at least one electrode is spaced apart from the encapsulation member.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 11, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Keunhyuk Lee, Oseob Jeon, Joon-seo Son, Seungwon Im
  • Patent number: 10985076
    Abstract: A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Greene, Victor W. C. Chan, Gangadhara Raja Muthinti
  • Patent number: 10985171
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, generally extending along the first horizontal direction, and laterally undulating along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 20, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Ryosuke Kaneko
  • Patent number: 10978667
    Abstract: A substrate to be encapsulated, an encapsulation assembly and a display device are provided. The substrate to be encapsulated comprises a base substrate, and a plurality of notches arranged in an array located in a region to be attached to an encapsulation layer, wherein the plurality of notches have a same shape of regular polygon.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 13, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Wanli Dong, Jibum Yang
  • Patent number: 10978367
    Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
    Inventors: Chiaki Kudou, Takashi Hasegawa, Kouichi Saitou
  • Patent number: 10978637
    Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Patent number: 10975464
    Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Yongan Xu, Abraham Arceo de la Pena, Chih-Chao Yang
  • Patent number: 10971604
    Abstract: Semiconductor devices and methods of forming the same include forming a second dielectric layer on sidewalls of a channel region of a semiconductor fin. The semiconductor fin is surrounded at a fin base by a first dielectric layer. The first dielectric layer is recessed to form a gap in the channel region of the semiconductor fin between the first dielectric layer and the second dielectric layer. Material from the semiconductor fin is etched away at the gap to separate the semiconductor fin from an underlying surface in the channel region. A gate stack is formed in the channel region that completely encircles the semiconductor fin.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10964705
    Abstract: In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 30, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Irfan Rahim, Raminda Madurawe
  • Patent number: 10937620
    Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua T. Smith, Benjamin Wunsch
  • Patent number: 10923286
    Abstract: A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Marina Zelner, Andrew Vladimir Claude Cervin, Edward Horne
  • Patent number: 10923453
    Abstract: A bonding apparatus for bonding a driving circuit to a display panel includes: a bonding stage unit on which the display panel is supported in bonding the driving circuit to the display panel; a head unit located above the bonding stage unit and with which ultrasonic waves are applied to the driving circuit to couple the driving circuit with a bonding area of the display panel supported on the bonding stage unit; and a protrusion disposed at an edge portion of the bonding stage unit, the edge portion corresponding to an end of the display panel at which the bonding area is disposed.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoung Yong Kim, Jeong Ho Hwang
  • Patent number: 10907253
    Abstract: A method includes forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) forming a first layer by supplying a precursor to the substrate; and (b) forming a second layer by supplying a reactant to the substrate and modifying the first layer. The (a) includes: (a-1) supplying the precursor to the substrate from a first supply part while supplying an inert gas at a first flow rate, and supplying an inert gas at a second flow rate from a second supply part; and (a-2) supplying the precursor to the substrate while supplying the inert gas at a third flow rate from the first supply part, or supplying the precursor from the first supply pan while stopping the supply of the inert gas, and supplying the inert gas at a fourth flow rate from the second supply part.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 2, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Hiroaki Hiramatsu, Shinya Ebata