Abstract: The present disclosure provides an image sensor and a method for manufacturing deep trench and through-silicon via of the image sensor, wherein: providing a pixel silicon wafer, performing a silicon wafer thinning on a second side of the pixel silicon wafer; forming a deep trench on the the second side of the pixel silicon wafer; filling the deep trench with organic material; coating photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a through-silicon via according to the through-silicon via pattern; depositing a dielectric protective layer on the surface of the deep trench and the surface of the through-silicon via; filling the deep trench with organic material; coating the photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a contact hole according to the contact hole pattern, depositing a barrier layer on the surface of the deep trench and the surface of the through-silicon v

Abstract: A method for semiconductor device fabrication includes forming storage elements on conductive structures. An interlevel dielectric (ILD) layer is formed over the storage elements. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.

Abstract: The present invention provides a wafer, semiconductor device and a method for manufacturing the same, in relation to the field of semiconductor technology. The wafer includes: a substrate; a dielectric layer, disposed on a surface of the substrate; a wafer acceptance test circuit, formed in the dielectric layer; a trench, formed in the dielectric layer and situated on a side of the wafer acceptance test circuit. The wafer acceptance test circuit may comprise a metal interconnection layer. The trench may be filled with a protective layer and has a depth greater than or equal to a depth of the wafer acceptance test circuit. When dicing dies along the scribe line area, the stress caused by dicing can be buffered and cracks may be reduced due to the elasticity of the protective layer. Moreover, the trench and the protective layer filled in the trench can prevent the cracks from extending, thereby improving the yield and stability of the dies.

Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

Abstract: An insulated-gate semiconductor device includes: an n+-type current spreading layer disposed on an n?-type drift layer; a p-type base region disposed on the current spreading layer; a n+-type main-electrode region arranged in an upper portion of the base region; an insulated-gate electrode structure provided in a trench; and a p+-type gate-bottom protection-region being in contact with a bottom of the trench, including a plurality of openings through which a part of the current spreading layer penetrates, being selectively buried in the current spreading layer, wherein positions of the openings cut on both sides of a central line of the trench are shifted from each other about the central line in a longitudinal direction of the trench in a planar pattern.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, wherein the first magnetic layer includes a first sub-magnetic layer, a second sub-magnetic layer, and a first intermediate layer between the first sub-magnetic layer and the second sub-magnetic layer, and the first sub-magnetic layer is provided between the nonmagnetic layer and the second sub-magnetic layer and has a magnetization direction antiparallel to a magnetization direction of the second sub-magnetic layer and has a magnetization amount smaller than that of the second sub-magnetic layer.

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

Abstract: A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Abstract: A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided.

Abstract: A light emitting device includes a light emitting element having an upper emission face, a lower face and a lateral face(s); a reflecting member having an upper face, a lower face and inner and outer lateral faces, wherein the inner lateral face(s) is disposed on the lateral face side of the light emitting element; a wavelength conversion member having an upper emission face, a lower face and a lateral face(s), wherein the lower face is disposed on the upper emission face of the light emitting element and on the upper face of reflecting member; and a cover member having inner and outer lateral faces, wherein the inner lateral face(s) completely covers the lateral face(s) of the wavelength conversion member. The cover member contains a reflecting substance and a coloring substance, and the body color of the wavelength conversion member and body color of the cover member are the same or similar in color.

Abstract: A display has a plurality of pixels in a matrix, the pixels each comprising a liquid crystal layer and/or light emitting diode layer, a plurality of substrates, at least a first substrate being optically transmissive to visible light, an electrode formed on one of the substrates and having electrically conductive material that has an electrical resistivity of less than 200 ?/sq and that comprises a siloxane material and particles having an average particle size of less than 10 microns.

Abstract: An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

Abstract: A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon nanotubes, wherein the first sheet and the second sheet are coupled in a stacked state, and the first carbon nanotubes and the second carbon nanotubes are different in an amount of deformation when pressure is applied.

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: A semiconductor photomultiplier includes a microcell, a photosensitive diode, and an anti-reflective coating. The microcell has an insulating layer formed over an active region. The photosensitive diode is formed in the active region beneath the insulating layer. The anti-reflective coating is provided on the insulating layer.