Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof.

Abstract: A semiconductor device includes first, second, third, and fourth active regions provided in an substrate, each of which includes a central portion, first and second portions provided at opposite sides of the central portion in a first direction, and third and fourth portions provided at opposite sides of the central portion in a second direction orthogonal to the first direction. An end portion of the first portion of the first active region faces a side portion of the fourth portion of the fourth active region, an end portion of which faces aside portion of the second portion of the second active region. An end portion of the second portion of the second active region faces a side portion of the third portion of the third active region, an end portion of which faces a side portion of the first portion of the first active region.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A process that incorporates teachings of the subject disclosure may include, for example, providing a first silicon dioxide layer on the silicon substrate, depositing a modifier layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide and annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide. The annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates. The first and second silicon dioxide layers have thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide. Other embodiments are disclosed.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.

Abstract: A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.

Abstract: Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

Abstract: Herein disclosed are systems and methods related to solid source chemical sublimator vessels and corresponding deposition modules. The solid source chemical sublimator can include a housing configured to hold solid chemical reactant therein. A lid may be disposed on a proximal portion of the housing. The lid can include a fluid inlet and a fluid outlet and define a serpentine flow path within a distal portion of the lid. The lid can be adapted to allow gas flow within the flow path. The solid source chemical sublimator can include a filter that is disposed between the serpentine flow path and the distal portion of the housing. The filter can have a porosity configured to restrict a passage of a solid chemical reactant therethrough.

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Abstract: A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

Abstract: A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

Abstract: A light emitting diode device comprising: a plurality of nanowires or nanopyramids grown on a graphitic substrate, said nanowires or nanopyramids having a p-n or p-i-n junction, a first electrode in electrical contact with said graphitic substrate; a light reflective layer in contact with the top of at least a portion of said nanowires or nanopyramids, said light reflective layer optionally acting as a second electrode; optionally a second electrode in electrical contact with the top of at least a portion of said nanowires or nanopyramids, said second electrode being essential where said light reflective layer does not act as an electrode; wherein said nanowires or nanopyramids comprise at least one group III-V compound semiconductor; and wherein in use light is emitted from said device in a direction substantially opposite to said light reflective layer.

Abstract: A method includes forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) forming a first layer by supplying a precursor to the substrate; and (b) forming a second layer by supplying a reactant to the substrate and modifying the first layer. The (a) includes: (a-1) supplying the precursor to the substrate from a first supply part while supplying an inert gas at a first flow rate, and supplying an inert gas at a second flow rate from a second supply part; and (a-2) supplying the precursor to the substrate while supplying the inert gas at a third flow rate from the first supply part, or supplying the precursor from the first supply part while stopping the supply of the inert gas, and supplying the inert gas at a fourth flow rate from the second supply part.

Abstract: A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.

Abstract: An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

Abstract: A shielding element comprises a rigid substrate and at least one electrically conductive two-dimensional structure which is placed on one of the faces of the substrate. The substrate and the electrically conductive two-dimensional structure are such that the shielding element has optical-transmission and shielding-efficiency values at least one of which varies between two zones of the shielding element. Such a shielding element enables easier assembly of a detection system comprising multiple optical sensors.

Abstract: A bonding apparatus for bonding a driving circuit to a display panel includes: a bonding stage unit on which the display panel is supported in bonding the driving circuit to the display panel; a head unit located above the bonding stage unit and with which ultrasonic waves are applied to the driving circuit to couple the driving circuit with a bonding area of the display panel supported on the bonding stage unit; and a protrusion disposed at an edge portion of the bonding stage unit, the edge portion corresponding to an end of the display panel at which the bonding area is disposed.