Patents Examined by Alexander Oscar Williams
  • Electronic devices utilizing contact pads with protrusions and methods for fabrication
    Patent number: 9257335
    Abstract: An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front-side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front-side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 9, 2016
    Assignee: Research Triangle Institute
    Inventors: Erik Vick, Garry Brian Cunningham, Dorota Temple
  • Surface mount package for a semiconductor integrated device, related assembly and manufacturing process
    Patent number: 9257372
    Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 9, 2016
    Assignees: STMicroelectronics (Mala) Ltd, STMicroelectronics Pte Ltd
    Inventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
  • Package vias for radio frequency antenna connections
    Patent number: 9252077
    Abstract: Via are described for radio frequency antenna connections related to a package. In one example, a package has a package substrate, a die attached to the package substrate, and a conductive via from the package substrate to an external surface of the package to make a radio frequency connection between the antenna and the package substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Wolfgang Molzer, Edmund Goetz, Reinhard Mahnkopf, Bernd Memmler
  • Connector and resin-sealed semiconductor device
    Patent number: 9252086
    Abstract: A connector for electrically connecting a chip electrode of a semiconductor element to a lead constituting an external leading terminal of the chip electrode, includes a first connecting part having an interface joined to the chip electrode; a second connecting part having an interface joined to a base end part of the lead; and a plate-shape coupling part for connecting the first connecting part and the second connecting part to each other, and having a step formed on the interface of the first connecting part in a direction away from the chip electrode by a half blanking process.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 2, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Atsushi Maruyama
  • Method for producing a structure for microelectronic device assembly
    Patent number: 9241403
    Abstract: Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 19, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Gabriel Pares
  • Semiconductor device including stacked semiconductor chips without occurring of crack
    Patent number: 9236335
    Abstract: A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: January 12, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Toru Ishikawa
  • Multi-chip socket
    Patent number: 9232681
    Abstract: A multi-chip socket includes a first cavity having a first support surface to support a first component including a first chip, the first support surface arranged to contact and support the first chip. A second cavity has a second support surface to support a second component including a second chip, the second support surface arranged to contact and support the second chip. The first support surface is in a first plane, and the second support surface is in a second plane, where the first plane is angled with respect to the second plane.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: January 5, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin B. Leigh, George D. Megason
  • Thermal management in electronic apparatus with phase-change material and silicon heat sink
    Patent number: 9230879
    Abstract: Embodiments of an electronic apparatus with a thermal management technique utilizing a silicon heat sink and/or a phase-change material, as well as an assembling method thereof, are described. In one aspect, the electronic apparatus comprises a main unit, a phase-change material and an enclosure enclosing the main unit and the phase-change material. The main unit comprises a substrate and at least one integrated-circuit (IC) chip disposed on the substrate. The phase-change material is in direct contact with each IC chip of the at least one IC chip to absorb and dissipate heat generated by the at least one IC chip.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 5, 2016
    Inventor: Gerald Ho Kim
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9224689
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 29, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9224690
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 29, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region
    Patent number: 9219072
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Fan-out semiconductor package
    Patent number: 9214434
    Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 15, 2015
    Inventors: Jin Young Kim, Doo Hyun Park, Seung Jae Lee
  • Interconnection structure of package structure and method of forming the same
    Patent number: 9209164
    Abstract: A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: December 8, 2015
    Assignee: Delta Electronics, Inc.
    Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin Lee
  • Semiconductor apparatus having through via capable of testing connectivity of through via
    Patent number: 9202802
    Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Heat Bit Park, Jong Chern Lee, Hong Gyeom Kim
  • Semiconductor devices having bit line structures disposed in trenches
    Patent number: 9202775
    Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: December 1, 2015
    Assignee: SK HYNIX INC.
    Inventors: Jin Ki Jung, Myoung Soo Kim
  • Word line coupling prevention using 3D integrated circuit
    Patent number: 9196582
    Abstract: A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to the first line. The word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuoyuan (Peter) Hsu
  • Method for generating die identification by measuring whether circuit is established in a package structure
    Patent number: 9196549
    Abstract: A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 24, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Kuang-Hui Tang
  • Semiconductor package having a heat slug and a spacer
    Patent number: 9190338
    Abstract: A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyol Park, Yunhyeok Im, Eon Soo Jang
  • Semiconductor device package adapter
    Patent number: 9184145
    Abstract: A semiconductor device packaged adapter for electrically coupling contacts on a first circuit member to contacts on a second circuit member. The adapter typically includes first and second substrates, each with arrays of terminals. Proximal ends of the first terminals on the first substrate are arranged to be soldered to the contacts on the first circuit member and proximal ends of the second terminals on the second substrate are arranged to be soldered to the contacts on the second circuit member. Complementary engaging structures located on distal ends of the first and second terminals engage to electrically and mechanically couple the first circuit member to the second circuit member.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: November 10, 2015
    Assignee: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Semiconductor device with bump adjustment and manufacturing method thereof
    Patent number: 9184143
    Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: November 10, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Yen-Ping Wang