Patents Examined by Alexander Oscar Williams
  • Integrated circuit packaging system with trace protection layer and method of manufacture thereof
    Patent number: 9177897
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a pre-plated leadframe having a contact protrusion and a protective pad on the contact protrusion; forming a contact pad and traces by etching the pre-plated leadframe; applying a trace protection layer on the contact pad, the traces, and the protective pad; removing the protective pad and a portion of the trace protection layer for exposing the contact pad; and depositing an external connector directly on a surface of the contact pad.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Henry Descalzo Bathan
  • Housing for an optoelectronic semiconductor component and method for producing such a housing
    Patent number: 9178332
    Abstract: A housing for an optoelectronic semiconductor component includes a housing body having a mounting plane and a leadframe with a first connection conductor and a second connection conductor. The housing body deforms the leadframe in some regions. The leadframe has a main extension plane which extends obliquely or perpendicularly with respect to the mounting plane. A semiconductor component having such a housing and a semiconductor chip and a method for producing a housing are also disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 3, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Uwe Strauss, Markus Arzberger
  • Chip package having sensing element and method for forming the same
    Patent number: 9177905
    Abstract: A chip package for a sensing element. The chip package includes a substrate having a first surface and a second surface, and a sensing layer having a sensing region disposed on the first surface of the substrate. A conducting pad structure is disposed on the substrate and electrically connected to the sensing region, and a spacer layer is disposed on the first surface of the substrate. A semiconductor substrate is place on the spacer layer. The semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region. A through-hole extends from a surface of the semiconductor substrate toward the substrate, and connects to the cavity.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: November 3, 2015
    Assignee: XINTEC INC.
    Inventors: Yu-Ting Huang, Tsang-Yu Liu
  • Sapphire structure with a concave portion including a metal substructure and method for producing the same
    Patent number: 9171899
    Abstract: A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: October 27, 2015
    Assignee: KYOCERA Corporation
    Inventors: Motohiro Umehara, Yoshinori Kubo
  • Electronic device incorporating a randomized interconnection layer having a randomized conduction pattern
    Patent number: 9171810
    Abstract: An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 27, 2015
    Assignee: NXP B.V.
    Inventors: Michael Antoine Armand in't Zandt, Viet Hoang Nguyen
  • Tall solders for through-mold interconnect
    Patent number: 9159690
    Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip package situated below a lower surface of a first substrate, the package including a die situated on a top surface of a second substrate, a molding disposed over the upper surface of the second substrate, the molding extending over the second die and including an opening extending from an upper surface of the molding towards an upper surface of the second substrate, wherein the opening is configured to admit at least a portion of the solder ball, and a solder column electrically and mechanically coupled to the second substrate, situated in the opening, conforming to the cylinder, and including at least two layers of solder with flux therebetween.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer
  • Device and method for reducing contact resistance of a metal
    Patent number: 9159666
    Abstract: A structure for an integrated circuit includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N2 flow at least 20 sccm.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Hung-Wen Su, Yu-Hung Lin, Kuei-Pin Lee, Yu-Min Chang
  • Interconnection structure having a via structure
    Patent number: 9159699
    Abstract: An interconnection structure is provided having a substrate with at least one electric device formed adjacent to a first side of the substrate and a via hole formed therethrough. The via hole has a first opening adjacent to the first side of the substrate. A via structure is disposed in the via hole without exceeding the first opening. A first pad is disposed on the first side of the substrate and covers the via hole. A second pad is disposed on a second side of the substrate opposite to the first side, wherein the via structure extends into the second pad. The first pad is adjoined to the via structure and electrically connects with the at least one electric device, and the first pad has a protrusion portion extending into the via hole.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 13, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hsin-Chang Tsai, Chia-Yen Lee, Peng-Hisn Lee
  • Semiconductor device for preventing a progression of a crack in a solder layer and method of manufacturing the same
    Patent number: 9153519
    Abstract: A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof and the insulating substrate is bonded to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern bonded to the heat-dissipating base member is formed such that a thickness of a circumferential portion of a bonding surface of the conductor pattern bonded to the insulating substrate is less than that of a center of the bonding portion.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 6, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Fumio Nagaune
  • Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections
    Patent number: 9142498
    Abstract: An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Boin Noh, Yonghwan Kwon, Sun-Hee Park
  • Chip package with improved heat dissipation and manufacturing method thereof
    Patent number: 9142529
    Abstract: A chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other, the semiconductor chip including an image sensor circuit; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; a bond pad formed on the upper surface, for electrically connecting with the image sensor circuit in the semiconductor chip, wherein the metal heat conductive layer conducts or absorbs heat generated by the semiconductor chip, to thereby reduce temperature of the image sensor circuit in the semiconductor chip and improve the performance of the circuit, wherein the metal heat conductive layer entirely covers the lower surface.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 22, 2015
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Yi-Chang Chang, Yen-Hsin Chen, Chi-Chih Shen
  • Semiconductor package stack having a heat slug
    Patent number: 9142478
    Abstract: A semiconductor package stack may include a lower semiconductor package and an upper semiconductor package stacked on a lower package board. The upper semiconductor package may include an upper semiconductor chip mounted on an upper package board with an opening configured to expose a lower surface of the upper semiconductor chip and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of a lower semiconductor chip.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Hoon Kim, Ji-Chul Kim, Seong-Ho Shin, In-Ho Choi
  • Semiconductor device with specific lead frame for a power semiconductor module
    Patent number: 9136209
    Abstract: A semiconductor device has a heat dissipating base; a patterned insulating substrate attached to the heat dissipating base with a solder therebetween; a semiconductor chip attached to a conductive pattern of the patterned insulating substrate with a solder therebetween; a first conductor attached to the semiconductor chip with a solder therebetween; a resin case attached to the heat dissipating base with an adhesive; and a second conductor attached to the first conductor by laser welding. The second conductor formed by rolling has stripe-shaped rolling traces formed on a surface thereof in a rolling direction and is disposed on the first conductor such that the rolling traces are arranged in a same direction.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 15, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toshiyuki Miyasaka
  • Solid hole array and method for forming the same
    Patent number: 9136160
    Abstract: A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 15, 2015
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Lijun Dong, Chao Zhao
  • Multi-chip packaging structure and method
    Patent number: 9129947
    Abstract: In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip can include a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads that can connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads that can connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 8, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xiaochun Tan, Wei Chen
  • Conductive contacts having varying widths and method of manufacturing same
    Patent number: 9105530
    Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar width, and the UBM width is greater than the pillar width.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
  • Semiconductor device including two groove-shaped patterns
    Patent number: 9105640
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 11, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kenichi Watanabe
  • Method for bonding of group III-nitride device-on-silicon and devices obtained thereof
    Patent number: 9105621
    Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: August 11, 2015
    Assignee: IMEC
    Inventors: Philippe Soussan, Melina Lofrano
  • Microelectronic packages having cavities for receiving microelectronic elements
    Patent number: 9105612
    Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 11, 2015
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Wael Zohni, Philip R. Osborn
  • Semiconductor memory apparatus for improving characteristics of power distribution network
    Patent number: 9105630
    Abstract: A semiconductor memory apparatus includes: a power distribution line disposed over a circumferential portion of a device formation region; a guard ring formed to surround the device formation region outside of the power distribution line; and one or more power reinforcement parts configured to electrically couple an edge part of the power distribution line to the guard ring.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 11, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Young Lee