Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor.

Abstract: According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.

Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Abstract: According to exemplary embodiments, a computer program product, system, and method for prefetching in memory include determining a missed access request for a first line in a first cache level and accessing an entry in a prefetch table, wherein the entry corresponds to a memory block, wherein the entry includes segments of the memory block. Further, the embodiment includes determining a demand segment of the segments in the entry, the demand segment corresponding to a segment of the memory block that includes the first line, reading a first field in the demand segment to determine if a second line in the demand segment is spatially related with respect to accesses of the demand segment and reading a second field in the demand segment to determine if a second segment in the entry is temporally related to the demand segment.

Abstract: According to exemplary embodiments, a computer program product, system, and method for prefetching in memory include determining a missed access request for a first line in a first cache level and accessing an entry in a prefetch table, wherein the entry corresponds to a memory block, wherein the entry includes segments of the memory block. Further, the embodiment includes determining a demand segment of the segments in the entry, the demand segment corresponding to a segment of the memory block that includes the first line, reading a first field in the demand segment to determine if a second line in the demand segment is spatially related with respect to accesses of the demand segment and reading a second field in the demand segment to determine if a second segment in the entry is temporally related to the demand segment.

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.

Abstract: Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R1) along a length of the bus line are also described.

Abstract: Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.

Abstract: A method for forming a thin film transistor includes steps of forming a first wiring layer over a first electrode layer and forming a second wiring layer over a second electrode layer, wherein the first electrode layer extends beyond an end portion of the first wiring layer, the second electrode layer extends beyond an end portion of the second wiring layer, and a semiconductor layer is formed so as to be electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer.

Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Abstract: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.

Abstract: Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the active regions and device isolation regions, conformally forming a preliminary gate insulating layer including silicon oxide on the active regions exposed in the grate trenches, nitriding the preliminary gate insulating layer using a radio-frequency bias having a frequency of about 13.56 MHz and power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride, forming a gate electrode material layer on the nitride preliminary gate insulating layer, partially removing the nitrided preliminary gate insulating layer and the gate electrode material layer to respectively form a gate insulating layer and a gate electrode layer, and forming a gate capping layer on the gate electrode layer to fill the gate trenches.

Abstract: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer serving as an antenna is provided in the same layer as a conductive layer of the transistor or the storage element. This characteristic makes it possible to omit an independent step of forming the conductive layer serving as an antenna and to conduct the step of forming the conductive layer serving as an antenna at the same time as the step of forming a conductive layer of another element. Therefore, the manufacturing step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.

Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Abstract: A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates.

Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.

Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.