Abstract: There is provided a light emitting device including: a package body having first and second circumferential surfaces and a plurality of side surfaces formed therebetween, the package body defined into first and second level areas including the first and second circumferential surfaces, respectively; first and second external terminal blocks each having an electrical contact part; an LED chip disposed between the first and second external terminal blocks in the first level area and having an electrode surface where first and second electrodes are formed; and wires electrically connected to first and second electrodes of the LED chip to the electrical contact parts of the first and second external terminal blocks, respectively.

Abstract: A method and apparatus for controlling heating and cooling of a transfer unit in a precision hot press device configured to suppress overheating and supercooling, and of performing quick heating and cooling, wherein the method and apparatus compares an amount of energy given to the transfer unit or taken from the transfer unit by a heating unit or a cooling unit with an amount of energy observed to enter into or exit from the transfer unit before the temperature of the transfer unit reaches a target temperature, calculates an amount of surplus or supercooled energy from a difference between the two energy amounts, and heats or cools the transfer unit based on the amount of surplus or supercooled energy.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: Mechanisms for identifying orientation of a sawed die are provided. By making metal pattern in the corner stress relief region in one corner of the die different from the other corners, users can easily identify the orientation of the die.

Abstract: A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body to singulate the plurality of imager devices and optics modules into individual units, each of which comprise an imager device and an optics module. A device is also disclosed which includes an imager device comprising a plurality of photosensitive elements and an optics module coupled to the imager device, the optics module comprising at least one lens that, when the optics module is coupled to the imager device, is positioned a fixed, non-adjustable distance from the plurality of photosensitive elements.

Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.

Abstract: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

Abstract: An organic light emitting display (OLED) device is disclosed. The OLED device includes a thin-film transistor (TFT), which includes a gate electrode; an active layer insulated from the gate electrode; source and drain electrodes insulated from the gate electrode and contacting the active layer; and an insulation layer interposed between the source and drain electrodes and the active layer; and an organic light-emitting element electrically connected to the TFT, wherein the insulation layer includes a first insulation sub-layer contacting the active layer; and a second insulation sub-layer formed on the first insulation sub-layer.

Abstract: An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.

Abstract: A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.

Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed.

Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Abstract: This invention relates to a process for forming a continuous pattern on a substrate with a liquid media. Upon the deposition of the liquid media on the substrate, a portion the continuous pattern is evaporated upon contact with the substrate.

Abstract: The present invention is aimed to provide an adhesive for bonding a semiconductor which has high transparency and facilitates recognition of a pattern or position indication on the occasion of semiconductor chip bonding. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein the amount of the inorganic filler in the adhesive is 30 to 70% by weight, the inorganic filler contains a filler A having an average particle size of less than 0.1 ?m and a filler B having an average particle size of not less than 0.1 ?m and less than 1 ?m, and the weight ratio of the filler A to the filler B is 1/9 to 6/4. The present invention is an adhesive for bonding a semiconductor containing: an epoxy resin; an inorganic filler; and a curing agent, wherein difference in refractive index is not more than 0.1 between the epoxy resin and the inorganic filler.

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.