Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: A system, to locate at least two storage devices from among a plurality of storage devices, receives a request for the data item. The request includes a data identifier for the data item. Next, the system generates a start number and a step number based on the data identifier. The system locates a first storage device utilizing the start number and, if the first storage device is available, the system reads the data item from the first storage device. However, if the first storage device is unavailable, the system utilizes the step number and the start number to compute a backup number that is utilized to locate a second storage device. If the second storage device is available, the system reads the data item from the second storage device.

Abstract: A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop of microcode instructions forming a microcode sequence. The microcode sequence is stored within a storage of a microcode unit. The method also includes storing a loop count value associated with the repetitive microcode instruction to a sequence control unit of the microcode unit. The method further includes determining a number of iterations to issue the microcode sequence for execution by an instruction pipeline based upon the loop count value. In response to receiving the repetitive microcode instruction, the method includes continuously issuing the microcode sequence for the number of iterations.

Abstract: In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.

Abstract: A data transfer control system includes a buffer controller that controls access to a data buffer and a transfer controller that controls data transfer between a PC connected to a BUS1 and the logical units LUN1 and LUN2 connected to a BUS2. The transfer controller includes: a command processing section that starts data transfer to or from the LUN1 based on a command indicated by an ORB for the LUN1 when the ORB is received, and starts data transfer to or from the LUN2 based on a command indicated by an ORB for the LUN2 when the ORB is receive; and a wait processing section that waits the processing of the ORB for the LUN2, when a bus reset occurs during the processing of the ORB for the LUN1 and the ORB for the LUN2 is received after the bus reset has occurred.

Abstract: Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing the work request, a work request ordering identifier for the work request is stored into an overflow structure. When the in-memory structure is capable of storing the work request, a recovery stub is generated for the work request ordering identifier, and the recovery stub is stored into the in-memory structure.

Abstract: A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the intermediate device is capable of communicating. In this embodiment, the intermediate device may be capable of controlling, at least in part, by the intermediate device, at least one data stream coming from the at least one storage device in accordance with at least one communication protocol. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A method and apparatus for executing a selective recovery after a branch misprediction is disclosed. In one embodiment, the instructions following the mispredicted branch point may be saved for selective re-execution in a buffer. Those instructions that wrote to physical registers between the mispredicted branch point and an exact convergence point, thereby causing false data dependencies, may be followed by corresponding move instructions to eliminate the false data dependencies. The instructions subsequent to the exact convergence point may then be selectively re-executed if subject to the previous false data dependencies.

Abstract: A microprocessor may include one or more functional units configured to execute operations, a scheduler configured to issue operations to the functional units for execution, and at least one replay detection unit. The scheduler may be configured to maintain state information for each operation. Such state information may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler should be replayed. If an instance of that operation is currently being executed by one of the functional units when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems may include such a microprocessor.

Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the compressed instruction data memory and forms program instructions which are supplied to the instruction cache. The program instructions are compressed in blocks of program instructions with an associated mask value where the bit values within the mask indicate whether corresponding bit slices within the blocks of program instructions are to be represented by a default bit value or a separately specified by bit slice specifier values. This technique is particularly well suited to VLIW processors.

Abstract: Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.

Abstract: A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the binary to detect its critical code regions, and the dynamic partitioning module partitions the binary into critical and non-critical code regions, re-implements the critical code regions in the configurable logic, and then transforms the binary so that it accesses the configurable logic rather than execute the critical code regions.

Abstract: Method for decreasing the existence of externally detectable revealing signals, so-called {umlaut over (R)}Ö{umlaut over (S)}, from keyboards (1), e.g. for computers, where the keyboard is fed with signals, so-called matrix signals, which are detected for detection of activity regarding the keys (2) of the keyboard, whereby said matrix signals are generated by means of signal devices. The method is especially characterized in that the matrix signals are high-frequency filtered before they are fed to the keyboard.

Abstract: A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller includes a first pin configured to enable access to one of a register of the display controller or a memory region of the display controller based upon a logical level of a first signal received by the first pin. A second pin is included. The second pin is configured to define the access to the register or the memory region as one of address information or data based upon a logical level of a second signal received by the second pin. The display controller includes an extra pin mode module configured to enable the first signal to select the data to access memory without accessing a register block. A device and methods for implementing an indirect addressing mode is also provided.

Abstract: Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

Abstract: A system and method for enabling remote management of data of devices using wireless communications. The system and method provides direct access to devices such as sensors from wireless devices having an integrated wireless transceiver and controller that are user programmable such a separate remote host controller is not required for managing the sensors. In one embodiment, a broadcast mode is provided wherein the wireless devices transmits a response for its corresponding sensors according to a predetermined sequence during a predetermined time slot according to a predetermined sequence.

Abstract: Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.