Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.

Abstract: A system identifies a document and obtains one or more types of history data associated with the document. The system may generate a score for the document based, at least in part, on the one or more types of history data.

Abstract: Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

Abstract: A semiconductor integrated circuit apparatus capable of reading out semiconductor information stored therein is provided. A semiconductor information storage section has semiconductor information unique to a semiconductor integrated circuit apparatus stored therein. The unique semiconductor information includes, for example, an identification number for identifying the semiconductor integrated circuit apparatus and information for identifying the time of manufacture such as a lot number. An externally provided storage apparatus has a readout program stored therein for reading the semiconductor information of the semiconductor integrated circuit apparatus as required.

Abstract: A method for operating a network of computing devices is disclosed. The method includes analyzing a network with a computing device having an addressing system to determine if a second addressing system is present on the network. The method also includes selectively providing a network address to a second computing device based on whether a second addressing system is present on the network.

Abstract: A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Abstract: As a user is drafting an electronic document (e.g., a word processing document, spreadsheet, etc.), the user may enter a predefined string of characters that represents a placeholder for information which is to be inserted into the document. A computerized system recognizes the predefined string of characters and, in response, automatically opens a messaging window that permits the user to request the information from one or more recipients. The message may include a portion of the electronic document surrounding the predefined string of characters to provide context for the recipients. A recipient can edit the context provided in the message to provide the requested information and transmit the message back to the user. If the user approves the edit made by the recipient, the computerized system may be configured to automatically integrate the edit into the electronic document.

Abstract: When all of a plurality of instructions are symmetry instructions, a symmetry instruction issuing unit issues the symmetry instructions to a plurality of reservation stations provided for every different arithmetic operating units until they become full. If it is determined that there is an asymmetry instruction among the plurality of instructions and the residual instructions are the symmetry instructions, an asymmetry instruction issuing unit 56 develops the asymmetry instruction into a multiflow of a previous flow and a following flow, issues the asymmetry instruction to the reservation station provided in correspondence to the specific arithmetic operating unit, and issues the residual symmetry instructions to the plurality of reservation stations provided for every different arithmetic operating units in an issuing cycle different from that of the asymmetry instruction until they become full.

Abstract: An application server blade for an embedded storage appliance is disclosed. The blade includes a printed circuit board (PCB) with a connector for connecting to a chassis backplane including a local bus. Affixed on the PCB is a server, a portion of a storage controller, and an I/O link coupling the server and storage controller portion. The server transmits packets on the I/O link to the storage controller portion. The packets include commands to transfer data to a storage device controlled by the storage controller. The storage controller portion receives the packets from the server on the I/O link and forwards the commands on the backplane local bus to another portion of the storage controller affixed on a separate PCB also enclosed in the chassis. The blade also includes a removal mechanism for hot-replacement of the blade in the chassis. The blade architecture facilitates software reuse.

Abstract: A method and mechanism for modifying computing resources in response to application behavior. A computing system includes a replication component configured to replicate data storage from a first data volume to a second data volume. In addition, the replication component is configured to monitor application I/O characteristics and store related statistics. I/O characteristics may include size, concurrency, locality, and frequency. I/O characteristics which are stored, and guidelines for modifying system resources based on those characteristics, may be displayed for use by an administrator in tuning system resources. Periodically, or in response to detecting an event, the replication component may automatically access the statistics and modify the system resources used by the replication system to better accommodate the application's behavior.

Abstract: A packet buffer management method and system are provided which enable maximum utilization of the hardware resources of the buffer memory, and which are optimum for the number of preset physical ports in use or for the number of service class (CoS) areas. In the buffer memory management method in a packet transmission/reception device, for storing a received packet in the buffer memory and controlling writing and reading of packets to and from the above buffer memory, the control methods are set in units of the service class contained in the header portion of received packets, and areas allocated to each service class in the buffer memory storing received packets are modified according to the set number of the above service classes.

Abstract: A hardware-controlled data protection scheme can be used on a device providing buffering between two different protocols, especially where at least one of the protocols does not use fixed length blocks. A fixed block size is arbitrarily imposed on the data in order to calculate a cyclical redundancy code (CRC) for the block. Block sizes are restricted to a value of 2n, e.g., 2, 4, 8, 16, etc. The device is able to time-share and to receive or send data on more than one port while sharing the CRC engine between the ports. Intermediate values of the CRC for a given port are temporarily saved in a CRC register file. As a block of data for a given port is completed, a final CRC value for the block is saved to a CRC random access memory (RAM) located on the device and the entry in the register file is cleared. When the data is then output from the device, the CRC for the block is recalculated and checked against the saved value to be sure that they match.

Abstract: The invention relates to a method for processing consistent data sets by asynchronous application of a subscriber in an isochronous, cyclical communication system. According to the invention, by connecting a communication memory and a consistency, transmission and reception buffer, copying processes leading ti delay can be kept to a minimum.

Abstract: Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An “add_pci” command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus.

Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

Abstract: A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.

Abstract: A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. The at least one issue logic unit may be operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit may be operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units according to respective ones of the multiple instructions.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.