Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.
Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a semiconductor substrate having photoelectric conversion elements. The photoelectric conversion elements form an N×N pixel array, where N is a positive integer larger than or equal to 3. The solid-state image sensor also includes a modulation layer disposed above the photoelectric conversion elements. The solid-state image sensor further includes a light-adjusting structure disposed on the modulation layer and corresponding to the N×N pixel array. The N×N pixel array includes a first pixel region having at least one first pixel. The N×N pixel array also includes a second pixel region adjacent to the first pixel region in a first direction and in a second direction different from the first direction and having second pixels. The aperture ratio of the first pixel and the aperture ratio of the second pixel are different.
Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
Abstract: A light-emitting device includes a base member, a plurality of light sources on or above an upper surface of the base member, and a reflector that comprises a plurality of surrounding portions. Each of the plurality of surrounding portions surrounds a respective one of the plurality of light sources in a plan view. Each of the plurality of surrounding portions has inclined lateral surfaces widened upward. Intervals between adjacent ones of the plurality of light sources are constant in the plan view. Upper peripheries of the inclined lateral surfaces of each of the plurality of surrounding portions define an opening having a substantially rectangular shape. The plurality of surrounding portions include a plurality of first surrounding portions and a plurality of second surrounding portions surrounding the plurality of first surrounding portions.
Abstract: An object is to provide a light-emitting element capable of emitting light with a high luminance even at a low voltage, and having a long lifetime. The light-emitting element includes n EL layers between an anode and a cathode (n is a natural number of two or more), and also includes, between m-th EL layer from the anode and (m+1)-th EL layer (m is a natural number, 1?m?n?1), a first layer including a first donor material in contact with the m-th EL layer, a second layer including an electron-transport material and a second donor material in contact with the first layer, and a third layer including a hole-transport material and an acceptor material in contact with the second layer and the (m+1)-th EL layer.
January 21, 2021
Date of Patent:
January 30, 2024
Semiconductor Energy Laboratory Co., Ltd.
Abstract: An image sensor includes a substrate, and a pixel separation pattern disposed in the substrate and interposed between a plurality of unit pixels. The plurality of unit pixels include a first unit pixel region and a second unit pixel region adjacent to the first unit pixel region in a first direction. The first unit pixel region and the second unit pixel region respectively include a first transfer gate and a second transfer gate. The pixel separation pattern includes a first pixel separation part interposed between the first unit pixel region and the second unit pixel region, and a second pixel separation part spaced apart from the first pixel separation part in the first direction. A top surface of the first pixel separation part is lower than a top surface of the second pixel separation part.
April 30, 2021
Date of Patent:
January 23, 2024
SAMSUNG ELECTRONICS CO., LTD.
Jameyung Kim, Tae-Hun Lee, Dongmo Im, Kwansik Cho
Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.
Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
Abstract: A shallow trench isolation (STI) structure and method of fabrication includes forming a shallow trench isolation (STI) structure having a polygonal shaped cross-section in a semiconductor substrate of an image sensor includes a two-step etching process. The first step is a dry plasma etch that forms a portion of the trench to a first depth. The second step is a wet etch process that completes the trench etching to the desired depth and cures damage caused by the dry etch process. A CMOS image sensor includes a semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation (STI) structure having a polygonal shaped cross-section.
Abstract: An OLED display panel, a manufacturing method thereof and a display device are provided. The OLED display panel includes an OLED display substrate and an encapsulation layer for encapsulating the OLED display substrate. The OLED display substrate includes a flexible base substrate, and a TFT layer, a planarization layer and an OLED element layer arranged sequentially on the flexible base substrate. At least one layer of the encapsulation layer, and at least one of the flexible base substrate or the planarization layer, are polymer material layers each doped with flexible nano-composite glass fibers.
Abstract: A semiconductor device includes: a base of a first nitride semiconductor; a buffer layer of a second nitride semiconductor provided on or above the base; a channel layer of a third nitride semiconductor provided on or above the buffer layer and having an opening portion; a barrier layer of a fourth nitride semiconductor provided on or above the channel layer; and an electrically conductive contact layer of a fifth nitride semiconductor provided in the opening portion and in contact with the buffer layer and the channel layer. A ratio of Al in a composition of the second nitride semiconductor is higher than or equal to that of the third nitride semiconductor. A ratio of Al in a composition of the first nitride semiconductor and a ratio of Al in a composition of the fourth nitride semiconductor are higher than that of the second nitride semiconductor.
Abstract: The technology relates to a semiconductor device including a hard mask easy to strip and capable of implementing a fine pattern with a high etch selectivity. According to an embodiment of the disclosure, a method for fabricating a semiconductor device comprises forming an etching target layer, forming a hard mask layer on the etching target layer, the hard mask layer including a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer, and etching the etching target layer using the hard mask layer as an etching barrier, wherein the second boron-doped silicon layer has a larger boron concentration than the first boron-doped silicon layer.
Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.
Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).
October 12, 2020
Date of Patent:
October 17, 2023
Micron Technology, Inc.
Daniel Billingsley, Jordan D. Greenlee, John D. Hopkins, Yongjun Jeff Hu, Swapnil Lengade
Abstract: A light emitting device is disclosed and includes an emission source configured to emit a primary blue light and a wavelength-converting element configured to convert the primary blue light to a secondary light, where the wavelength-converting element including a red phosphor material having a peak emission wavelength that is less than 620 nm and a green phosphor material having a peak emission wavelength that is greater than 530 nm. The device may have a correlated color temperature (CCT) in the range of 1600K-2500K, may exhibit a melanopic/photopic ratio less than 0.25 and/or may exhibit a radiometric power fraction of light having a wavelength below 530 nm below 0.1.
Abstract: An image sensor is includes a plurality of pixels. Each of the pixels includes a silicon photoconversion region and a material that at least partially surrounds the photoconversion region. The material has a refraction index smaller than the refraction index of silicon, and the interface between the photoconversion region of the pixel and the material is configured so that at least one ray reaching the photoconversion region of the pixel undergoes a total reflection or a plurality of successive total reflections at the interface.
Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor substrate having a top surface, a semiconductor layer on the top surface of the semiconductor substrate, a light-absorbing layer on a portion of the semiconductor layer, and a doped region in the portion of the semiconductor layer. The doped region is positioned in the portion of the semiconductor layer adjacent to the light-absorbing layer.
May 4, 2021
Date of Patent:
October 10, 2023
GlobalFoundries Singapore Pte. Ltd.
Ping Zheng, Eng Huat Toh, Kiok Boone Elgin Quek, Kien Seen Daniel Chong, Jing Hua Michelle Tng
Abstract: An etching method for performing side-etching of silicon germanium layers of a substrate having alternating silicon layers and the silicon germanium layers formed thereon is provided. The method includes modifying surfaces of residuals by supplying a plasmarized gas containing hydrogen to the residuals on exposed end surfaces of the silicon germanium layers, and performing side-etching on the silicon germanium layers by supplying a fluorine-containing gas to the silicon germanium layers.