Abstract: A display panel may include a first display substrate and a second display substrate on the first display substrate. The second display substrate may include a plurality of pixel regions and a peripheral region adjacent to the pixel regions. The second display substrate may include a first color control pattern configured to emit light of a first color, a second color control pattern spaced apart from the first color control pattern in a first direction and configured to emit light of a second color different from the first color, and first and second light-blocking patterns in the peripheral region between the first and second color control patterns. The first and second light-blocking patterns may be spaced apart from each other, in a second direction crossing the first direction, to define a gap region.

Abstract: The solid-state image sensor includes a semiconductor substrate having first and second photoelectric conversion elements, a color filter layer, and a hybrid layer. The isolation structure is disposed between the first and second photoelectric conversion elements. The color filter layer is disposed above the semiconductor substrate. The hybrid layer is disposed between the semiconductor substrate and the color filter layer. The hybrid layer includes a first partition structure, a second partition structure, and a transparent layer. The first partition structure is disposed to correspond to the isolation structure. The second partition structure is surrounded by the first partition structure. The transparent layer is between the first partition structure and the second partition structure. The refractive index of the first partition structure and the refractive index of the second partition structure are lower than the refractive index of the transparent layer.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a conductive layer in the substrate and having a surface exposed by the substrate. A groove is formed in the substrate and adjacent to the conductive layer, and a sidewall of the groove exposes a portion of a sidewall surface of the conductive layer. The semiconductor structure also includes a lower electrode layer located in the groove and on a top surface of the conductive layer. The lower electrode layer covers the top surface and the portion of the sidewall surface of the conductive layer.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a plurality of pixel sensors, an isolation grid disposed in the substrate and separating the plurality of pixel sensors from each other, a reflective grid disposed over the isolation grid on the back side of the substrate, an a low-n grid disposed over the back side of the substrate and overlapping the reflective grid from a top view. A width of the low-n grid is greater than a width of the reflective grid.

Abstract: A CMOS sensor includes a silicon material having a surface periodic structure of silicon portions and non-silicon portions, formed by multiple supercells repeated in a 2-dimensional lattice pattern. Each image pixel of the sensor has at least 2×2 supercells. The lattice constants in both lateral directions are within a range defined by a wavelength of the light to be sensed. Within each supercell, the non-silicon portions create an effective refractive index for the light that changes gradually with depth. The non-silicon portions within the supercell have lateral feature sizes smaller the wavelength of the light to be sensed, and vertical feature sizes larger than the wavelength of the light to be sensed. In some examples, each supercell includes at least two inverted pyramids having different base sizes and/or different heights. A dielectric material fills the non-silicon portions of the periodic structure and covers the silicon material.

Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.

Abstract: A system and method for etching workpieces in a uniform manner are disclosed. The system includes a semiconductor processing system that generates a ribbon ion beam, and a workpiece holder that scans the workpiece through the ribbon ion beam. The workpiece holder includes a plurality of independently controlled thermal zones so that the temperature of different regions of the workpiece may be separately controlled. In certain embodiments, etch rate uniformity may be a function of distance from the center of the workpiece, also referred to as radial non-uniformity. Further, when the workpiece is scanned, there may also be etch rate uniformity issues in the translated direction, referred to as linear non-uniformity. The present workpiece holder comprises a plurality of independently controlled thermal zones to compensate for both radial and linear etch rate non-uniformity.

Abstract: A processing method of a device wafer includes a mask coating step of coating a front surface of the device wafer with a water-soluble resin, a mask forming step of applying a laser beam along each division line, forming a groove, and removing a protective mask and a functional layer to expose a substrate, a plasma etching step of forming a division groove that divides the substrate along the groove by supplying a gas in a plasma condition, an expanding step of expanding a protective tape in a plane direction to expand a width of the division groove, an adhesive film dividing step of applying a laser beam along the division groove to divide the adhesive film that has been exposed due to the formation of the division groove, and a cleaning step of cleaning and removing the water-soluble resin.

Abstract: Provided is an image sensor including a semiconductor substrate including a first surface and a second surface and a plurality of pixel regions spaced apart, the plurality of pixel regions including a first region including a plurality of image pixels configured to generate image data and a second region including a plurality of phase difference detection pixels configured to perform autofocusing, a first grid pattern including a plurality of groove portions disposed on the second surface, a plurality of first microlenses selectively disposed on bottom surfaces of the plurality of groove portions corresponding to at least one of the first region and the second region, a plurality of color filters filling the plurality of groove portions, respectively, a second grid pattern superimposed on the first grid pattern, and a plurality of second microlenses separated by the second grid pattern and disposed on the plurality of color filters, respectively.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, an isolation structure surrounding the pixel sensor and disposed in the substrate, a dielectric layer disposed over the pixel sensor on the front side of the substrate, and a plurality of conductive structures disposed in the dielectric layer and arranged to align with the isolation structure.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and having a plurality of first color filter segments. The solid-state image sensor further includes a second color filter layer disposed adjacent to the first color filter layer and having a plurality of second color filter segments. The solid-state image sensor includes a first grid structure disposed between the first color filter layer and the second color filter layer. The first grid structure has a first grid height. The solid-state image sensor also includes a second grid structure disposed between the first color filter segments and between the second color filter segments. The second grid structure has a second grid height that is lower than or equal to the first grid height.

Abstract: A substrate carrier is described that uses a proportional thermal fluid delivery system. In one example the apparatus includes a heat exchanger to provide a thermal fluid to a fluid channel of a substrate carrier and to receive the thermal fluid from the fluid channel, the thermal fluid in the fluid channel to control the temperature of the carrier during substrate processing. A proportional valve controls the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve in response to the measured temperature to adjust the rate of flow.

Abstract: Methods and apparatus for cleaving a substrate in a semiconductor chamber. The semiconductor chamber pressure is adjusted to a process pressure, a substrate is then heated to a nucleation temperature of ions implanted in the substrate, the temperature of the substrate is then adjusted below the nucleation temperature of the ions, and the temperature is maintained until cleaving of the substrate occurs. Microwaves may be used to provide heating of the substrate for the processes. A cleaving sensor may be used for detection of successful cleaving by detecting pressure changes, acoustic emissions, changes within the substrate, and/or residual gases given off by the implanted ions when the cleaving occurs.

Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Abstract: A semiconductor device is proposed. The semiconductor device includes a semiconductor body including a first main surface. A plurality of trench electrode structures extend in parallel along a first lateral direction. A first one of the plurality of trench electrode structures includes a gate electrode. A gate contact is electrically connected to the gate electrode in a gate contact area. The gate contact area is arranged in a first section along the first lateral direction. An isolation structure is arranged between the gate contact and the semiconductor body in the gate contact area. A bottom side of the isolation structure is arranged between a bottom side of the first one of the plurality of trench electrode structures and the first main surface along a vertical direction. The gate contact extends up to or below the first main surface along the vertical direction.

Abstract: An image sensor is disclosed. The image sensor includes a plurality of photodiodes arranged in first and second directions in a matrix, a plurality of first isolation layers, each two adjacent first isolation layers arranged in the first direction being spaced apart from each other by a first distance, each first isolation layer being interposed between adjacent photodiodes arranged in the second direction, and a plurality of second isolation layers, each two adjacent second isolation layers arranged in the second direction being spaced apart from each other by a second distance, each second isolation layer being interposed between adjacent photodiodes arranged in the first direction.

Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a bit line structure on a top surface of the substrate; forming a spacer structure on the bit line structure, the spacer structure including a sacrificial layer sandwiched by a first dielectric layer and a second dielectric layer; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a seal layer to seal the gap.