Patents Examined by Ali Naraghi
  • Patent number: 10847620
    Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Goryu, Mitsuaki Kato, Kenji Hirohata
  • Patent number: 10847688
    Abstract: A light emitting device includes a base having a conductor wiring, at least one light emitting element mounted on the base and electrically connected to the conductor wiring, and a light transmissive sealing member. The light transmissive sealing member includes a light diffusion material. The light transmissive sealing member covers the at least one light emitting element. The light transmissive sealing member has a projection shape. The projection shape has a substantially circular bottom surface facing the base and a height in a light axis direction of the at least one light emitting element. The height is greater than a diameter of the substantially circular bottom surface. The light transmissive sealing member has a maximum length when the light transmissive sealing member is viewed from the light axis direction. The diameter of the substantially circular bottom surface is smaller than the maximum length of the light transmissive sealing member.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 24, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Motokazu Yamada, Yuichi Yamada
  • Patent number: 10847366
    Abstract: Methods for depositing a transition metal chalcogenide film on a substrate by cyclical deposition process are disclosed. The methods may include, contacting the substrate with at least one transition metal containing vapor phase reactant comprising at least one of a hafnium precursor, or a zirconium precursor, and contacting the substrate with at least one chalcogen containing vapor phase reactant. Semiconductor device structures including a transition metal chalcogenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Miika Mattinen, Mikko Ritala, Markku Leskelä
  • Patent number: 10847525
    Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate, and a depression region is formed between two adjacent isolation structures. A conductive layer and a sacrificial layer are conformally formed on the isolation structures and the substrate. The sacrificial layer in the depression region defines a recess part. A first CMP process is performed to partially remove the sacrificial layer and to expose the conductive layer on the isolation structures. A second CMP process is performed to partially remove conductive layer, and to expose top surfaces of the isolation structures. A third CMP process is performed to remove the sacrificial layer completely. A top surface of the conductive layer is level with a top surface of the isolation structure after the third CMP process.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: November 24, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yi-Chung Chen, Cheng-Jen Lai
  • Patent number: 10840028
    Abstract: The present disclosure relates to a preparing method of a large-area perovskite thin film, comprising: forming an organic metal halide-alkylamine compound by exposing an organic metal halide compound having a perovskite structure to an alkylamine gas; preparing a coating solution by adding a solvent on the organic metal halide-alkylamine compound; and preparing a perovskite thin film by coating the coating solution on a substrate.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 17, 2020
    Assignees: Research & Business Foundation Sungkyunkwan University, GLOBAL FRONTIER CENTER FOR MULTILSCALE ENERGY SYSTEMS
    Inventors: Nam Gyu Park, Dong Nyuk Jung
  • Patent number: 10837607
    Abstract: A light emitting device is disclosed and includes an emission source configured to emit a primary blue light and a wavelength-converting element configured to convert the primary blue light to a secondary light having a correlated color temperature (CCT) in the range of 1600K-2500K and color rendering index (CRI) in the range of 40-60, the wavelength-converting element including a red phosphor material having a peak emission wavelength that is less than 620 nm and a green phosphor material having a peak emission wavelength that is greater than 530 nm. The device may exhibit a melanopic/photopic ratio of less than 0.25 and/or may exhibit a radiometric power fraction of light having a wavelength below 530 nm below 0.1.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Lumileds LLC
    Inventors: Wouter Soer, Hans-Helmut Bechtel
  • Patent number: 10832351
    Abstract: A sensing system bias is reduced across a first agricultural machine and a second agricultural machine. A collection of agronomic data is accessed, that is indicative of an estimated crop yield. The collection that is accessed, for example, includes at least a first set of data sensed by the first agricultural machine and a second set of data sensed by the second agricultural machine. In addition, the first and second sets of data can be scaled based on a yield correction factor. A bias between the scaled first set of data and the scaled second set of data is determined, and a smoothing operation is performed on the scaled first and second sets of data.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: November 10, 2020
    Assignee: Deere & Company
    Inventors: Sebastian Blank, Robert A. Stevens, Dohn W. Pfeiffer, Noel W. Anderson, James J. Phelan
  • Patent number: 10833154
    Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 10, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Steven M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
  • Patent number: 10825826
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 3, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Patent number: 10818791
    Abstract: Sacrificial gate structures are simultaneously formed in isolation regions that are wider than the sacrificial gate structures formed in the active region. The wider sacrificial gate structures are formed by taking advantage of a smaller lateral etch of p-type silicon than undoped or n-type doped silicon during reactive ion etching. Amorphous or polycrystalline silicon is used as a sacrificial pattern transfer patterning layer in the gate patterning process. The p-type amorphous or polycrystalline silicon increases the sacrificial gate structure length in the isolation region and thus reduces spacing between the sacrificial gate structures in the isolation region. During inner spacer formation, the inner spacers pinch-off all sacrificial gate structures in the isolation region preventing the shallow trench isolation structure to be undercut and thus preventing the collapsing of the sacrificial gate structures in the isolation region.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10818755
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 27, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10811468
    Abstract: A display device includes a display panel having a display area and a color filter layer including a black matrix and a color filter. Peripheral areas and a center area are in the display area. Light emitting areas and a non-light emitting area are in the display area. A center black matrix is in the non-light emitting area of the center area, and a peripheral black matrix is in the non-light emitting area of the peripheral area. Center color filters are in the light emitting areas of the center area, and peripheral color filters are in the light emitting areas of the peripheral area. First and second adjacent light emitting areas are in the peripheral area. First and second peripheral color filters are respectively in the first and second light emitting areas, and overlap each other in the non-light emitting area between the first and second light emitting areas.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyeonbum Lee
  • Patent number: 10804131
    Abstract: There is provided a carrier plate removing method of removing a carrier plate from a workpiece disposed on a front surface of the carrier plate with a provisional bond layer interposed between the carrier plate and the workpiece. The carrier plate removing method includes a first holding step of holding the carrier plate and exposing the workpiece, a stepped portion forming step of forming a stepped portion in which an back surface side projects outward of a front surface side at an outer peripheral edge of the carrier plate, a second holding step of holding the workpiece and exposing the carrier plate, and a carrier plate removing step of removing the carrier plate from the workpiece by applying a force to the stepped portion and moving the carrier plate in a direction of being separated from the workpiece by a removing unit.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: October 13, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hayato Kiuchi, Katsuhiko Suzuki
  • Patent number: 10804386
    Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung
  • Patent number: 10797156
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10784327
    Abstract: A display device is disclosed, which includes: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate; and a second transistor disposed above the substrate. The first transistor includes: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode. In addition, the second transistor includes: a second semiconductor layer. Herein, one of the first semiconductor layer and the second semiconductor layer includes a first silicon semiconductor layer, and the other includes a first oxide semiconductor layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chandra Lius, Kuan-Feng Lee, Nai-Fang Hsu
  • Patent number: 10784345
    Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 22, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
  • Patent number: 10784233
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10777640
    Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
  • Patent number: 10770522
    Abstract: An EL device includes a display panel and an imaging element, and the display panel includes a panel substrate and an EL layer, and an imaging hole for guiding light from a subject to the imaging element is formed in the display area to straddle a plurality of scanning signal lines and a plurality of data signal lines when viewed from a direction perpendicular to a display area.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tetsuya Ueno