Patents Examined by Ali Naraghi
  • Patent number: 11328929
    Abstract: Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 10, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yueh Sheng Ow, Junqi Wei, Wen Long Favier Shoo, Ananthkrishna Jupudi, Takashi Shimizu, Kelvin Boh, Tuck Foong Koh
  • Patent number: 11329131
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti, Alfio Guarnera
  • Patent number: 11329089
    Abstract: Pixel isolation wells in a semiconductor image sensor are implemented via two or more photoresist patterning phases and two or more corresponding dopant implantation operations. A distinct photomask is applied in each patterning phase with the isolation-well street lines patterned by each mask spaced from one another by an integer multiple (i.e., 2 or greater) of the pixel pitch, and patterns formed by respective masks being staggered by the pixel pitch.
    Type: Grant
    Filed: June 7, 2020
    Date of Patent: May 10, 2022
    Assignee: Gigajot Technology, Inc.
    Inventor: Jiaju Ma
  • Patent number: 11315969
    Abstract: The present application provides a buried tri-gate fin vertical gate structure. Which includes a transfer transistor on an epitaxial layer; a photodiode in the epitaxial layer at one side of the transfer transistor. A reset transistor on the epi-layer includes N+ regions at both sides of its gate, one of the N+ regions forms a floating diffusion node. The bottom of the fin vertical gate protrudes into the epitaxial layer with a number of vertical portions. Thus, increased surface areas enhance charge motion at the bottom, combining large-area transfer at an upper layer by the vertical gate and quick transfer at the bottom by the FINFET, thereby improving photo response.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 26, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Zhi Tian, Juanjuan Li, Hua Shao, Haoyu Chen
  • Patent number: 11316012
    Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface facing each other in a thickness direction, the first main surface including a trench. The trench has a predetermined depth in the thickness direction and has a substantially wedge shape that has a first side surface and a second side surface that face each other and are not parallel to each other, and a first end surface and a second end surface that face each other and are substantially parallel to each other. The first side surface and the second side surface intersect each other at a line, or extension surfaces of the first side surface and the second side surface extended in the thickness direction intersect each other at a line, and the line extends in a first direction that does not align with a cleavage plane of the semiconductor substrate.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koichi Nishita, Masaki Takeuchi, Yutaka Takeshima, Kazuhiro Inoue
  • Patent number: 11310924
    Abstract: A display device includes a window substrate having a top surface and a bottom surface, a display panel under the window substrate, an opening being defined in the display panel, a light blocking portion directly on the bottom surface of the window substrate and surrounding the opening when viewed from a plan view, and an electronic component overlapping with the opening.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 19, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyongbin Jin
  • Patent number: 11309342
    Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor including a dummy vertical transistor structure underlying a photodetector. The pixel sensor includes a substrate having a front-side surface opposite a back-side surface. The photodetector is disposed within the substrate. A deep trench isolation (DTI) structure extends from the back-side surface of the substrate to a first point below the back-side surface. The DTI structure wraps around an outer perimeter of the photodetector. The dummy vertical transistor structure is laterally spaced between inner sidewalls of the DTI structure. The dummy vertical transistor structure includes a dummy vertical gate electrode having a dummy conductive body and a dummy embedded conductive structure. The dummy embedded conductive structure extends from the front-side surface of the substrate to a second point vertically above the first point and the dummy conductive body extends along the front-side surface of the substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 11302789
    Abstract: A semiconductor structure and a formation method thereof are provided. The semiconductor structure includes: a semiconductor substrate having a source region or drain region therein. The source region or drain region has a groove. The semiconductor structure can include a metal silicide layer arranged on a surface of a sidewall of the groove and an insulating layer arranged on a bottom surface of the groove. The edge of the insulating layer is in contact with a bottom surface of the metal silicide layer on the sidewall of the groove; and a conducting layer filled in the groove and arranged on the metal silicide layer and the insulating layer. The semiconductor structure of the present disclosure can prevent electric current from leaking into the semiconductor substrate at the bottom of the source/drain region.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 12, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11302782
    Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
  • Patent number: 11302806
    Abstract: The present invention discloses a double-gate trench-type insulated-gate bipolar transistor device. A first trench and a second trench, which are located in a P-type doped well layer, and separate from each other, are extended into a lightly-doped N-type drift layer. A heavily-doped P-type source region and a heavily-doped N-type source region, which are sequentially connected, are located between the first trench and the second trench, and are arranged at an upper part of the P-type doped well layer in a horizontal direction. The heavily-doped P-type source region is located at a periphery of the second trench, a middle part and the upper part of the P-type doped well layer are provided with an N-type doped well layer and a P-type doped base region layer, respectively. The heavily-doped P-type source region and the heavily-doped N-type source region are both located at an upper part of the P-type doped base region layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 12, 2022
    Assignee: HUGE POWER LIMITED TAIWAN BRANCH (B.V.I.)
    Inventors: Jia-Ming Kuo, Chung-Wei Yu, Kuo-Lun Huang, Chao-Tsung Chang
  • Patent number: 11302741
    Abstract: An image sensor structure has a visible light detection region and an infrared light detection region neighboring the visible light detection region. The image sensor structure includes a semiconductor substrate, photo sensing members, an infrared absorption enhancing member, a color filter and an infrared pass filter. The semiconductor substrate has a front side and a back side opposite to each other. The first photo sensing member is disposed in the front side of the semiconductor substrate. The infrared absorption enhancing member is in the back side of the semiconductor substrate and only in the infrared light detection region. The color filter is over the back side of the semiconductor substrate and in the visible light detection region. The infrared pass filter is over the infrared absorption enhancing member.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: April 12, 2022
    Inventors: Amit Mittra, Yang Wu, Ki-Hong Kim
  • Patent number: 11302536
    Abstract: A deflectable platen including a first layer formed of a material having a first coefficient of thermal expansion (CTE), and a second layer bonded to the first layer and having a second CTE, the second layer including a plurality of electrodes embedded therein for facilitating electrostatic clamping of wafers to the second layer, wherein the second CTE is different than the first CTE.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 12, 2022
    Assignee: APPLIED Materials, Inc.
    Inventors: Ming Yin, Dawei Sun
  • Patent number: 11296138
    Abstract: A backside illuminated image sensor includes a substrate having a frontside surface, a backside surface and a recess formed in a backside surface portion thereof, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, an anti-reflective layer disposed on the backside surface of the substrate, and a second bonding pad disposed in the recess and electrically connected with the bonding pad. The anti-reflective layer includes a metal oxide layer disposed on the backside surface of the substrate, a first silicon insulating layer disposed on the metal oxide layer, and a second silicon insulating layer disposed on the first silicon insulating layer. The second silicon insulating layer includes a first portion disposed on an inner side surface of the recess and a second portion disposed on a bottom surface of the recess.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 5, 2022
    Assignee: DB HITEK CO., LTD.
    Inventors: Chang Hun Han, In Guen Yeo, Jong Man Kim, Seong Jin Kim
  • Patent number: 11289585
    Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11289530
    Abstract: A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 29, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Patent number: 11289635
    Abstract: The light emitting diode display apparatus comprises a pixel disposed on a substrate and configured to display an image. The pixel includes a first light emitting portion configured to connect with a first gate line disposed in a first direction, a data line disposed in a second direction which is perpendicular to the first direction, and a first driving power line which is parallel to the data line, a second light emitting portion configured to connect a second gate line which is parallel to the first gate line, the data line, and the first driving power line, a common connection pattern configured to connect with the first light emitting portion and the second light emitting portion in common, and a third light emitting portion configured to connect between the second driving power line and the common connection pattern. Some of the common connection pattern is configured to overlap with the second driving power line.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 29, 2022
    Assignee: LG Display Co., Ltd.
    Inventor: HyeonHo Son
  • Patent number: 11282883
    Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Patent number: 11282875
    Abstract: An image sensor may include a first shared pixel region and a first isolation layer on a substrate, the first isolation layer defining the first shared pixel region. The first shared pixel region may include photo-sensing devices in sub-pixel regions and a first floating diffusion region connected to the photo-sensing devices. The sub-pixel regions may include a first sub-pixel region and a second sub-pixel region that constitute a first pixel group region. The sub-pixel regions may include a third sub-pixel region and a fourth sub-pixel region that constitute a second pixel group region. The first shared pixel region may include first and second well regions doped with first conductivity type impurities. The second well region may be spaced apart from the first well region. The first pixel group region may share a first well region. The second pixel group region may share the second well region.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eunsub Shim
  • Patent number: 11282982
    Abstract: A light-emitting device, includes: a substrate, including a base with a main surface; and a plurality of protrusions on the main surface, wherein the protrusion and the base include different materials; and a semiconductor stack on the main surface, including a side wall, and wherein an included angle between the side wall and the main surface is an obtuse angle; wherein the main surface includes a peripheral area surrounding the semiconductor stack, and the peripheral area is devoid of the protrusion formed thereon.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 22, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Wen-Hsiang Lin, Pei-Chi Chiang, Yi-Wen Ku
  • Patent number: 11276684
    Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei