Abstract: A display device including: a first data line arranged in a display area of a substrate and extending in a first direction; a second data line arranged in the display area and extending in the first direction; a connecting line arranged in the display area and including a first portion parallel to the first data line, a third portion parallel to the second data line, and a second portion between the first portion and the third portion, wherein the connecting line is electrically connected to the second data line; and an auxiliary line overlapping the first data line or the second data line.

Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes steps of providing a cavity structure, the cavity structure including a seed area including a seed material. The method further includes growing, within the cavity structure, a first embedding layer in a first growth direction from a seed surface of the seed material. The method includes further steps of removing the seed material, growing, in a second growth direction, from a seed surface of the first embedding layer, a quantum dot structure and growing, within the cavity structure, on a surface of the quantum dot structure, a second embedding layer in the second growth direction. The second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

Abstract: A method of fabricating a display device may include forming a preliminary first pixel definition layer by coating a first material on a base substrate including a first electrode, forming a first pixel definition layer by forming a first opening in the preliminary first pixel definition layer, the first opening exposing the first electrode, performing a plasma treatment on the first pixel definition layer, forming a preliminary organic layer by providing a first organic material, forming a preliminary second pixel definition layer by coating a second material on the first pixel definition layer, forming a second pixel definition layer by forming a second opening in the preliminary second pixel definition layer, the second opening overlapping with the first opening, and forming an organic layer by providing a second organic material. A thickness of the organic layer may be greater than a thickness of the preliminary organic layer.

Abstract: A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a number of first semiconductor layers that are vertically spaced apart from one another, a second S/D structure coupled to a first end of the first semiconductor layers; and a third S/D structure coupled to a second end of the first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

Abstract: A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.

Abstract: An image sensing device includes a semiconductor substrate, a material layer, a lens layer, and a lens capping layer. The semiconductor substrate includes a pixel region, which include a plurality of unit pixels, and a pixel-array peripheral region located outside of and peripheral to the pixel region. The material layer is disposed over the semiconductor substrate in the pixel region and the pixel-array peripheral region, and includes a first trench extending to a predetermined depth in the pixel-array peripheral region. The lens layer is disposed over the material layer in the pixel region and collects incident light into a unit pixel in the pixel region. The lens capping layer is disposed over the lens layer and the material layer and includes an edge region formed to fill the first trench.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.

Abstract: An image sensor including contiguous color filters is disclosed. The image sensor includes a grid disposed between color filters, a first reflective layer disposed over an upper portion of the grid and patterned to include first reflective structures at borders between adjacent sensor pixels to reflect light, and a second reflective layer disposed over and spaced from the first reflective layer and patterned to include second reflective structures at borders between adjacent sensor pixels to reflect light, and each second reflective structure formed in an angular shape to direct reflected light incident to borders between adjacent sensor pixels into adjacent sensor pixels.

Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

Abstract: A solid-state image pickup device includes: a filter section including filters that are disposed corresponding to respective pixels, and each allowing light of a color that corresponds to corresponding one of the pixels to transmit therethrough, in which the pixels are each configured to receive the light of the predetermined color; and a microlens array section including a plurality of microlenses each configured to collect the light for corresponding one of the pixels, in which the microlenses are stacked with respect to the filter section, and are arranged in an array pattern corresponding to the respective pixels. The microlenses have two or more shapes that are different from one another corresponding to the respective colors of the light to be received by the pixels, and each having an end that is in contact with the end of adjacent one of the microlenses.

Abstract: A display device includes a 1-1st wiring including a 1-1st end at an end portion thereof in a first direction, a 1-2nd wiring extending in a second direction opposite to the first direction and including a 1-2nd end that is apart from the 1-1st end, a second wiring that is apart from the 1-1st wiring and the 1-2nd wiring, a first bridge wiring in contact with the 1-1st wiring and the 1-2nd wiring and electrically connecting the 1-1st wiring to the 1-2nd wiring, and a third wiring extending in the first direction and disposed such that the second wiring is between the 1-1st wiring and the third wiring. The first bridge wiring has a convex shape in a direction opposite to a direction from the 1-1st wiring and the 1-2nd wiring to the second wiring.

Abstract: An image sensor is disclosed. The image sensor includes a first pixel of a first color arranged alternately with a pixel of a second color in a first direction of a pixel array, a second pixel of the first color arranged alternately with a pixel of a third color in the first direction in a row different from that of the first pixel of the first color, an isolation layer formed to surround the first pixel in the pixel array and structured to have a first depth, and an isolation layer formed to surround the second pixel in the pixel array and structured to have a second depth different from the first depth. One of the first and second pixels of the first color, and each of the pixels of the second color and the third color are configured to selectively receive different colors of light, respectively.

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.

Abstract: An image sensing device includes a substrate, a first reflector, and at least one second reflector. The substrate includes a photoelectric conversion element corresponding to each unit pixel. The first reflector is disposed in a manner that at least some parts of the first reflector overlap with the photoelectric conversion element, and is configured to reflect incident light directed to the photoelectric conversion element in a direction away from the photoelectric conversion element. The second reflect disposed over the substrate is configured to reflect the incident light reflected by the first reflector in a direction along which the incident light moves again closer to the photoelectric conversion element.

Abstract: An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, and a passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. A method for forming an image sensor with passivated full deep-trench isolation includes forming trenches in a semiconductor substrate, filling the trenches with a sacrificial material, forming a plurality of photodiode regions, forming a circuit layer, thinning the semiconductor substrate, and removing the sacrificial material. A method for reducing noise in an image sensor includes removing material from a semiconductor substrate to form a plurality of trenches that extend from a front surface toward a back surface, and depositing a dielectric material onto the back surface and into the plurality of trenches through a back opening of each trench.

Abstract: A semiconductor device includes a semiconductor substrate, a fin-shaped structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin-shaped structure is disposed on and extends upwards from a top surface of the semiconductor substrate in a vertical direction. The gate structure is disposed straddling a part of the fin-shaped structure. At least a part of the first doped region is disposed in the fin-shaped structure. The second doped region is disposed in the fin-shaped structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin-shaped structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than or coplanar with a top surface of the first doped region in the vertical direction.

Abstract: Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.