Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.

Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

Abstract: A method of manufacturing a thin film transistor includes: forming an active pattern on a substrate; forming an insulating layer and a gate electrode layer on the active pattern in order; forming a photoresist pattern on the gate electrode layer; forming a preliminary gate electrode by wet etching the gate electrode layer using the photoresist pattern; forming an insulating pattern by dry etching the insulating layer using the photoresist pattern and the preliminary gate electrode; and forming a gate electrode by wet etching a side surface of the preliminary gate electrode using the photoresist pattern.

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device has a substrate in which recess regions are formed and semiconductor regions acting as a source region or a drain region is defined between the recess regions; a gate insulating layer disposed on an inner surface of each recess region; a recess gate disposed on the gate insulating layer in each recess region; an insulating capping layer disposed above the recess gate in each recess region; a metallic insertion layer disposed between a side surface of the recess gate and a side surface of the insulating capping layer and facing with a side surface of the source region or the drain region; and an intermediate insulating layer disposed between the metallic insertion layer and the recess gate to electrically insulate the metallic insertion layer from the recess gate.

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: A multi-pixel detector of an image sensor is described. The multi-pixel detector includes a first photodiode region disposed within a semiconductor substrate to form a first pixel, a second photodiode region disposed within the semiconductor substrate to form a second pixel adjacent to the first pixel, and a partial isolation structure extending from a first side of the semiconductor substrate towards a second side of the semiconductor substrate between the first photodiode region and the second photodiode region. A length of a lateral portion of the partial isolation structure between the first photodiode region and the second photodiode region is less than a lateral length of the first photodiode region.

Abstract: A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A display device includes an electrode, a protection layer disposed on the electrode, and an encapsulation organic layer disposed on the protection layer. In a first area, an edge of the encapsulation organic layer is spaced a first distance from an edge of the electrode, and the edge of the encapsulation organic layer is spaced a second distance from an edge of the protection layer. In the second area, the edge of the encapsulation organic layer is disposed between the edge of the electrode and the edge of the protection layer. In the second area, the edge of the encapsulation organic layer is spaced a third distance, greater than the first distance, from the edge of the electrode, and the edge of the encapsulation organic layer is spaced a fourth distance, greater than the second distance, from the edge of the protection layer.

Abstract: An image sensor includes a substrate having a first surface and a second surface facing each other. A deep trench extends from the first surface to the second surface of the substrate and defines a pixel region within the substrate. A photoelectric conversion region is disposed within the pixel region. A shallow trench extends from the first surface of the substrate into the substrate and at least partially defines a pattern within the pixel region. In a plan view, the pattern has a first corner, a second corner facing the first corner in a first diagonal direction, a third corner, and a fourth corner facing the third corner in a second diagonal direction that crosses the first diagonal direction. In the plan view, a radius of curvature of the third corner is less than a radius of curvature of the first corner.

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Abstract: An image sensor including: a substrate which includes a first surface and a second surface opposite each other; a plurality of pixels, each pixel including a photoelectric conversion layer in the substrate; a pixel separation pattern disposed in the substrate and separating the pixels; a surface insulating layer disposed on the first surface of the substrate; conductor contacts disposed in the surface insulating layer; and a grid pattern disposed on the surface insulating layer, wherein the pixel separation pattern includes a first portion and a second portion arranged in a direction parallel to the first surface of the substrate, and the conductor contacts are interposed between the first portion of the pixel separation pattern and the grid pattern and are not interposed between the second portion of the pixel separation pattern and the grid pattern.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: The display panel includes a plurality of light-emitting areas and a plurality of non-light-emitting areas, the plurality of light-emitting areas being space apart from each other by the plurality of non-light-emitting area; light-emitting elements each located in one of the plurality of light-emitting areas and including an anode and a cathode that are opposite to each other, and a light-emitting layer located therebetween; a cover layer covering a light-emission side of the light-emitting element. The cover layer includes a substrate and first dopants doped in the substrate, the first dopants are magnetic. When an external magnetic field intensity applied to the cover layer is changed by an amount greater than a preset magnetic field intensity, the first dopants in the substrate are rearranged from a first mode to a second mode.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a semiconductor substrate having photoelectric conversion elements. The photoelectric conversion elements form an N×N pixel array, where N is a positive integer larger than or equal to 3. The solid-state image sensor also includes a modulation layer disposed above the photoelectric conversion elements. The solid-state image sensor further includes a light-adjusting structure disposed on the modulation layer and corresponding to the N×N pixel array. The N×N pixel array includes a first pixel region having at least one first pixel. The N×N pixel array also includes a second pixel region adjacent to the first pixel region in a first direction and in a second direction different from the first direction and having second pixels. The aperture ratio of the first pixel and the aperture ratio of the second pixel are different.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.

Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.