Abstract: Quantum dots and methods of making quantum dots are described. A method begins with forming quantum dots having a core-shell structure with a plurality of ligands on the shell structure. The method includes exchanging the plurality of ligands with a plurality of second ligands. The plurality of second ligands have a weaker binding affinity to the shell structure than the plurality of first ligands. The plurality of second ligands are then exchanged with hydrolyzed alkoxysilane to form a monolayer of hydrolyzed alkoxysilane on a surface of the shell structure. The method includes forming a barrier layer around the shell structure by using the hydrolyzed alkoxysilane as a nucleation center.

Abstract: An organic light emitting display device realizes slimness, having flexibility, and effectively reducing or preventing visibility of reflected external light, which includes an organic light emitting panel, a first adhesive layer on the organic light emitting panel, a touch electrode array being in contact with the first adhesive layer, a separation layer on the touch electrode array, and a cover film on the separation layer.

Abstract: A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1?z1As, the first window layer includes Alz2Ga1?z2As, and z1>z2.

Abstract: A display device including a first substrate and a pixel defining layer disposed on the first substrate. The pixel defining layer is configured to define an emissive area and a transmissive area. The display device also includes a first electrode disposed in the emissive area, a light emitting layer disposed on the first electrode, and a second electrode disposed in the emissive area and the transmissive area. The second electrode includes an oxide layer in the transmissive area.

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

Abstract: An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, and a configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

Abstract: In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

Abstract: A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main surface of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.

Abstract: A light-emitting electrode having a ZnO transparent electrode and a method for manufacturing the same are provided. A light-emitting element according to an embodiment comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a ZnO transparent electrode, which is positioned on the second conductive semiconductor layer, which makes an Ohmic contact with the second conductive semiconductor layer, and which comprises monocrystalline ZnO, wherein the diffraction angle of a peak of the ZnO transparent electrode, which results from X-ray diffraction (XRD) omega 2theta (?2?) scan, is in the range of ±1% with regard to the diffraction angle of a peak of the second conductive semiconductor layer, which results from XRD ?2? scan, and the FWHM of a main peak of the ZnO transparent electrode, which results from XRD omega (?) scan, is equal to or less than 900 arc sec.

Abstract: A phase change material for a phase change memory and a preparing method thereof. The phase change material for a phase change memory has a chemical formula of Sc100-x-y-zGexSbyTez, wherein 0?x?60, 0?y?90, 0<z?65, 0<100-x-y-z<100. The phase change material for a phase change memory according to the present invention is capable of repeatedly changing phases. The Sc100-x-y-zGexSbyTez has two different resistance value states, i.e., a high resistance state and a low resistance state, and a reversible transformation between the high resistance state and the low resistance state can be achieved by being applied a pulse electrical signal thereto, which satisfies basic requirements of a storage material for the phase change memory.

Abstract: A Light Emitting Device (LED) that has increased reliability and efficiency. Specifically, the LED may be formed using Atomic Layer Deposition to improve the thermal conductivity between the ceramic plate and the LED, decrease the amount of organic contamination, and increase the efficiency of the optical output of the LED.

Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.

Abstract: This present disclosure provides an array substrate, a manufacturing method thereof, and a display apparatus, aiming at solving the issue of light reflection on the array substrates and improving the display effects of display apparatuses. The array substrate includes a transparent substrate; a plurality of components disposed on a first side of the transparent substrate; and a shielding pattern, disposed on a second side of the transparent substrate, and configured to shield light reflected from a surface of at least one of the plurality of components.

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

Abstract: A method of forming a three-dimensional transistor device may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may include directing angled oxygen ions at the CMOS nanosheet device structure. As a result an oxide may be formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, while an oxide is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack. The method may include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.