Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.

Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, facilitate creation and use of 3D models of objects with different material properties. In one aspect, a method includes specifying a continuous data format representation for a first property of an object and a discretized data format representation for a second property of the object, wherein the first property and the second property are different from each other; producing a 3D model of the object within a 3D space using the continuous and discretized data format representations, which overlap with each other in all three dimensions in at least a portion of the 3D space; and using at least one common access method into the 3D model of the object to obtain data from both the continuous and discretized data format representations, within the portion of the 3D space, to manufacture the object using one or more manufacturing processes.

Abstract: Structures and formation methods of a light sensing device are provided. The light sensing device includes a semiconductor substrate and a filter element over the semiconductor substrate. The light sensing device also includes a light sensing region below the filter element and a light shielding element over the semiconductor substrate and surrounding a lower portion of the filter element. The light sensing device further includes a dielectric element over the light shielding element and surrounding an upper portion of the filter element. A top width of the light shielding element and a bottom width of the dielectric element are different from each other.

Abstract: A display may have an array of pixels. Each pixel may have a light-emitting diode such as an organic light-emitting diode. The organic light-emitting diodes may each have an anode that is coupled to a thin-film transistor pixel circuit for controlling the anode. Transparent windows may be formed in the display. The windows may be formed by replacing data storage capacitors and other pixel circuit structures in a subset of the pixels with transparent window structures, by selectively removing portions of light-emitting diode anodes, and by shifting anodes. An array of electrical components such as an array of light sensors may be aligned with the transparent windows and may be used to measure light passing through the transparent windows.

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

Abstract: A semiconductor package substrate has a cavity on the land side among the ball-grid array, and a support structure inserted into the cavity as well as covering at least one device that is seated on the land side. The cavity is an enclave or an exclave. The support structure takes on several useful compositions as well as shapes and sizes.

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.

Abstract: A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25.

Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Abstract: A light emitting device includes a semiconductor light emitting element; and a light reflective member having a multilayer structure and covering the side faces of the semiconductor light emitting element. The light reflective member includes: a first layer disposed on an inner, semiconductor light emitting element side, the first layer comprising a light-transmissive resin containing a light reflective substance, and a second layer disposed in contact with an outer side of the first layer, the second layer comprising a light-transmissive resin containing the light reflective substance at a lower content than that of the first layer.

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

Abstract: An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.

Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.

Abstract: The present invention provides an automated modular system and method for production of biopolymers including DNA and RNA. The system and method automates the complete production process for biopolymers. Modular equipment is provided for performing production steps with the individual modules arrange in a linear array. Each module includes a control system and can be rack mounted. One side of the array of modules provides connections for power, gas, vacuum and reagents and is accessible to technicians. On the other side of the array of modules a robotic transport system is provided for transporting materials between module interfaces. The elimination of the requirement for human intervention at multiple steps in the production process significantly decreases the costs of biopolymer production and reduces unnecessary complexity and sources of quality variation.

Abstract: A light emitting diode display includes a plurality of display units and a plurality of auxiliary display units. The display units are arranged in an array and connected to each other. Each of the display units has a device arrangement region, a peripheral region surrounding the device arrangement region, and a plurality of first light emitting devices disposed on the device arrangement region and arranged in an array. The auxiliary display units are disposed on the peripheral regions of the display units. Each of the auxiliary display units includes an auxiliary substrate and a plurality of second light emitting devices arranged in an array. The second light emitting devices are disposed on the auxiliary substrate and located at a level different from a level of the first light emitting devices. Each of the auxiliary substrates is across adjacent two of the display units.

Abstract: An image sensing apparatus includes a first substrate structure, a second substrate structure, and a memory chip. The first substrate structure includes a pixel region having a photoelectric conversion element. The second substrate structure includes a first surface connected to the first substrate structure and a second surface opposite the first surface, and also includes a circuit region to drive the pixel region. The memory chip is mounted on the second surface of the second substrate structure. The first substrate structure and the second substrate structure are electrically connected by first connection vias passing through the first substrate structure. The second substrate structure and the memory chip are electrically connected by second connection vias passing through a portion of the second substrate structure. The first connection vias and the second connection vias are at different positions on a plane.