Abstract: A light-emitting diode (LED) chip and a display device having the same are provided. A green LED is regrown on a blue LED to produce blue and green light, and a red phosphor is disposed on the blue or green LED to produce red light. Red light, green light, and blue light are to be produced using a single LED chip. The single LED chip forms three subpixels therein so as to facilitate a transfer process of the LED chip to a display panel. The LED chip is configured based on the blue, green, and blue LEDs so as to facilitate the fabrication and driving of the LED chip.

Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

Abstract: A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).

Abstract: A multi-layered conductor comprising one or more conductor layers of an electrically conductive material and one or more shielding layers of a soft magnetic material. The shielding layer can be coated onto the conductor layer and has a lower conductivity and a higher magnetic permeability than the electrically conductive material of conductor layers. The shielding layer can, at least when alternating current (AC) flows through the multi-layered conductor at relatively high frequencies, provide a separate power path for at least a portion of the high frequency AC current, as well as absorb at least a portion of the high frequency noises associated with that separated high frequency AC current. Additionally, the shielding layer can be separated from the conductor layer at an output end of the multi-layered conductor so that output ends of the shielding layer and conductor layer can be electrically connected to different electrical devices or components.

Abstract: A light-emitting device includes a metal connecting structure; a metal reflective layer on the metal connecting structure; a barrier layer between the metal connecting structure and the metal reflective layer; a light-emitting stack on the metal reflective layer; a dielectric layer between the light-emitting stack and the metal reflective layer, and a first extension electrode and a second extension electrode on the light-emitting stack and away from the metal reflective layer. The dielectric layer includes a first part and a second part separated from the first part from a cross section of the light-emitting device. The first extension electrode and the second extension electrode respectively align with the first part and the second part. From a cross section of the light-emitting stack, the first extension electrode has a first width and the first part has a second width larger than the first width.

Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

Abstract: A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*1015 cm?3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*1022 cm?4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.

Abstract: A TMR element includes a base layer that is disposed on an upper surface of a via interconnect part, a magnetic tunnel junction that is disposed on a surface of the base layer, and an interlayer insulation layer that covers a side surface of each of the via interconnect part and the base layer. The base layer includes a stress relieving region. The magnetic tunnel junction includes a reference layer having a magnetization fixed direction, a magnetization free layer, and a tunnel barrier layer disposed between the reference layer and the magnetization free layer. The interlayer insulation layer includes an insulation material.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

Abstract: A micro-LED display panel including a substrate, a plurality of micro-LEDs, and a plurality of reinforced structures is provided. The micro-LEDs are disposed at a side of the substrate, wherein each of the micro-LEDs comprises an epitaxial layer and an electrode layer electrically connected to the epitaxial layer, and the electrode layer are located between the epitaxial layers and the substrate. Each of the micro-LEDs is electrically connected to the substrate through the corresponding electrode layer. Each of electrode layers includes a first electrode and a second electrode. The reinforced structures are disposed between the micro-LEDs and the substrate respectively, and each of the reinforced structures is located between the corresponding the first electrode and the second electrode. A Young's modulus of each of reinforced structures is smaller than a Young's modulus of the corresponding electrode layer.

Abstract: Disclosed are a display device and a method of manufacturing a display device. The method of a display device according to an exemplary embodiment of the present disclosure includes: a first transferring step of transferring a plurality of LEDs disposed on a wafer onto a plurality of donors; and a second transferring step of transferring the plurality of LEDs transferred onto the plurality of donors onto a display panel, in which in the second transferring step, an area where one of the plurality of donors overlaps the display panel partially overlaps an area where the other one of the plurality of donors overlaps the display panel. Therefore, the plurality of LEDs having different wavelengths is uniformly transferred to reduce a boundary caused by the difference in wavelengths and improve color uniformity.

Abstract: A fan-out line component, a display device comprising the same, and a fan-out line wiring method are disclosed. The fan-out line component is used for signal connection between a first functional region and a second functional region. A channel in an intermediate section of a channel wire outlet end of the first functional region is a dummy channel. A first wiring from an effective signal channel in the first functional region which is closest to the dummy channel to the second functional region extends to a central normal region of the dummy channel, and then extends in the central normal region along a direction of a central normal.

Abstract: A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.

Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.

Abstract: A light emitting element according to one embodiment can comprise: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a light-transmitting ohmic layer on the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; and a second electrode on the light-transmitting ohmic layer. The light emitting element can include two first sides facing each other, and two second sides facing each other. The width of the first side is greater than the width of the second side, and the first side and the second side can be perpendicular to each other. The distance between the first branch electrode and the second branch electrode is ? to ½ of the width of the second side of either one thereof.

Abstract: A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.

Abstract: Embodiments of a display device including barrier layer coated quantum dots and a method of making the barrier layer coated quantum dots are described. Each of the barrier layer coated quantum dots includes a core-shell structure and a hydrophobic barrier layer disposed on the core-shell structure. The hydrophobic barrier layer is configured to provide a distance between the core-shell structure of one of the quantum dots with the core-shell structures of other quantum dots that are in substantial contact with the one of the quantum dots. The method for making the barrier layer coated quantum dots includes forming reverse micro-micelles using surfactants and incorporating quantum dots into the reverse micro-micelles. The method further includes individually coating the incorporated quantum dots with a barrier layer and isolating the barrier layer coated quantum dots with the surfactants of the reverse micro-micelles disposed on the barrier layer.

Abstract: A memory element includes a free magnetization layer (“FR-ML”) in a film form, a nonmagnetic layer (“NML”), and a fixed magnetization layer (“FX-ML”), The NML and FX-ML are stacked on the FR-ML. The FR ML stores a single bit of data “0” or “1” according to a magnetization direction and rewrites the data by reversing the magnetization direction. An antiferromagnet that exhibits the anomalous Hall effect and has a reversible magnetization direction is used for the FR-M. The reversal of the magnetization direction of the FR-ML is performed using the FX-ML by the spin-transfer torque technique. To read data, a reading current is caused to flow in one direction, and a Hall voltage generated in the FR-ML by the anomalous Hall effect is extracted from the FR-ML. The polarity of the Hall voltage is reversed in accordance with the magnetization direction of the FR-ML.

Abstract: A method of fabricating a vertically stacked nanosheet semiconductor device includes epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. The method includes performing at least three reactive ion etch processes forming recesses. The method includes forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses. The method includes growing a first epitaxial layer on the source or drain regions, forming at least three pFET structures. The method includes etching away a portion of each of the pFET structures and depositing a dielectric layer on each. The method includes growing a second epitaxial layer, forming at least three nFET structures. Each layer of the pFET structure and nFET structure are stacked vertically and each layer of the pFET structure and nFET structures have independent source or drain contacts.