Patents Examined by Alpesh M. Shah
  • Patent number: 6035104
    Abstract: An e-mail system implemented on a server having a network connection receives and forwards e-mail messages based on subscriber-supplied criteria. When a message is received addressed to the subscriber, characteristics of the message, such as existence of and size of attachments, are compared to characteristics previously supplied by the subscriber. If a match is found, the subscriber is notified, such as by a page to a pager carried by the subscriber, of the message and the nature of the match.. Facility is provided at the server for the subscriber to then call the server, log on, and provide instructions for forwarding the matched message. Forwarding may be to such as a hand-held device or a notebook computer operated by the subscriber, or to a mailbox or mailboxes on other servers, or any combination. A subscriber is then in control of points of delivery of incoming e-mail messages.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: March 7, 2000
    Assignee: Data Link Systems Corp.
    Inventor: Manuel Zahariev
  • Patent number: 5954813
    Abstract: A data processor such as an integrated circuit microcontroller (10) includes a central processing unit (12), a system integration module (14), and on-chip peripherals (16, 24, 28, 30) commonly connected by an information bus (32). The microcontroller (10) supports transparent background mode operation by not only preserving the state of the central processing unit (12), but also the states of on-chip peripherals (16, 24, 28, 30). For example, a serial peripheral interface (16) has a status register (86) with some status bits which are cleared in normal mode by reading the status register (86). In background mode, reading the status register (86) does not cause the status bits to be cleared. The system integration module (14) has a control bit, known as the break clear flag enable (BCFE) bit, which selectively allows the states of the on-chip peripherals (16, 24, 28, 30) to be altered when the microcontroller is in background mode.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: September 21, 1999
    Assignee: Motorola, Inc.
    Inventors: Shari L. Mann, David J. A. Pena, Charles F. Studor, Gordon W. McKinnon
  • Patent number: 5946496
    Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector registers from nodes together form an architectural vector register having architectural vector elements. The mapping vector defines an assignment of architectural vector elements to physical vector elements for its node. The memories from the nodes together form an aggregate memory.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: August 31, 1999
    Assignee: Cray Research, Inc.
    Inventors: Rabin A. Sugumar, Stefanos Kaxiras
  • Patent number: 5930523
    Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: July 27, 1999
    Assignees: Hitachi Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
  • Patent number: 5926642
    Abstract: An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: July 20, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John G. Favor
  • Patent number: 5923893
    Abstract: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: July 13, 1999
    Assignee: Motorola, Inc.
    Inventors: William C. Moyer, John Arends, Jeffrey W. Scott
  • Patent number: 5923894
    Abstract: A pin control unit and a plurality of addressable storage locations are provided to an integrated circuit to control the input/output (I/O) pins of a functional block of the integrated circuit or the I/O pins of the integrated circuit. Multiple ones of the addressable storage locations are correspondingly coupled to I/O buffers associated with the I/O pins. The pin control unit selectively loads bit values into appropriate ones of the addressable storage locations. In response, the I/O buffers input bit values from and/or output bit values to the corresponding I/O pins. The pin control unit controls subsets of the I/O pins in a coordinated manner as I/O ports. The pin control unit also controls data movement between the addressable storage locations and various temporary storage elements of the functional block/integrated circuit.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: July 13, 1999
    Assignee: TeraGen Corporation
    Inventor: Donald L. Sollars
  • Patent number: 5913071
    Abstract: A peripheral device and a host device implement a scalar interrupt-acknowledgement system. The peripheral device detects events and increments an unprocessed counter in response to each detected event. The host device processes the events and increments a processed counter in response to each processed event. After a number of events have been processed, the host device transmits the value held by the processed counter to the peripheral device. In response, the peripheral device subtracts the value of the processed counter from the value of the unprocessed counter. The peripheral device asserts an interrupt when events remain to be processed and deasserts the interrupt when all the events have been processed.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: June 15, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Robert Macomber
  • Patent number: 5913069
    Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: June 15, 1999
    Assignee: Cray Research, Inc.
    Inventors: Rabin A. Sugumar, Stefanos Kaxiras
  • Patent number: 5901323
    Abstract: A controller of the type used in process control includes a plurality of modular I/O units. The I/O units includes I/O circuits which may be of four basic types: digital input circuits, digital output circuit, analog input circuits and analog output circuits. Each of the I/O circuits has a code generator that generates a binary code indicating the type of I/O circuit. The controller is microprocessor-controlled and periodically communicates with the I/O circuits and determines the type of each I/O unit based upon the binary code. The I/O units may be temperature-compensated based upon the temperature within the housing of the controller, and other integrity checks may be performed on the I/O units. The controller also has a change module routine which allows the I/O units to be installed or removed during operation of the controller.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: May 4, 1999
    Assignee: Fisher Controls International, Inc.
    Inventors: Jon B. Milliken, Richard J. Vanderah, Dennis G. Sickels
  • Patent number: 5889963
    Abstract: A polling procedure providing the capabilities to assign and dynamically modify a user's communication parameters (i.e., response allocation and polling rate) based on the user's bandwidth requirements. In addition, the polling procedure instructs the users to delay their responses as a function of round-trip propagation delay and remaining response allocation for previously polled users to ensure that poll responses from separate users do not overlap.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: March 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Inder Sarat Gopal, Roch Andre Guerin, Kumar Nellicherry Sivarajan
  • Patent number: 5887181
    Abstract: The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. The data signals are represented as unsigned 8-bit binary values. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a maximum overflow state or a minimum overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is in the maximum or minimum overflow state.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: March 23, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Vladimir Y. Volkonsky
  • Patent number: 5884027
    Abstract: A multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge. The invention consolidates a high performance processor, a PCI to PCI bus bridge, PCI bus-processor address translation unit, direct memory acces's (DMA) controller, memory controller, secondary PCI bus arbitration unit, inter-integrated circuit (I.sup.2 C) bus interface unit, advanced programmable interrupt (APIC) bus interface unit, and a messaging unit into a single system which utilizes a local memory. The PCI bus is an industry standard high performance, low latency system bus. The PCI to PCI bridge provides a connection path between two independent 32-bit PCI buses and provides the ability to overcome PCI electrical loading limits. The addition of the local processor brings intelligence to the PCI bus bridge.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: March 16, 1999
    Assignee: Intel Corporation
    Inventors: Elliot Garbus, Peter Sankhagowit, Marc Goldschmidt, Nick Eskandari
  • Patent number: 5881218
    Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: March 9, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Amit D. Sanghani, Narayanan Sridhar
  • Patent number: 5875339
    Abstract: An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back from the output of the arbiter circuit. At any point in time, only one of the plurality of MUTEX elements is selected based on the current state of the grant signals. The selected MUTEX element is used to arbitrate and grant one user exclusive access to a shared resource among the one or more users requesting exclusive access to the shared resource. All the other MUTEX elements in the arbiter circuit are disabled and are inactive during this time. After issuing the grant signal, the selected MUTEX element is disabled and a new MUTEX element responsible for issuing the next grant signal is selected based the new state of the grant signals.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: February 23, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Charles E. Molnar, Ian W. Jones
  • Patent number: 5875301
    Abstract: An electronic system interconnect. The interconnect includes a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: February 23, 1999
    Assignee: Apple Computer, Inc.
    Inventors: William S. Duckwall, Michael D. Teener
  • Patent number: 5872986
    Abstract: A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 16, 1999
    Assignee: Intel Corporation
    Inventor: Jay S. Heeb
  • Patent number: 5872993
    Abstract: The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: February 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Glen W. Brown
  • Patent number: 5872989
    Abstract: A method and apparatus for handling a large-capacity register file by using a small instruction field as to support a software pipeline. The invention includes a register file having a plurality of physical registers corresponding to a plurality of physical register numbers and a converter which converts logical register numbers included in instructions to be executed into physical register numbers. A physical register, which is used when a logical register is accessed as a result of execution of an instruction, is specified by a pointer corresponding to the logical register number included in the instruction. The pointer used for the access is incremented if so specified in the instruction to ensure that subsequent instructions making access to the same logical register use different physical registers.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: February 16, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Tsushima, Yoshikazu Tanaka, Yoshiko Tamaki
  • Patent number: 5872921
    Abstract: A computerized analyzer for a transactional data stream prepares feed records from the data stream, the feed records comprising all transaction records received in a finite time slice. A new feed record is prepared for each passing time slice, and, in a preferred embodiment, new time slices are generated during operation based on record volume received during a previous time slice. The feed records are condensed to significant feed records by selecting only those transaction records in each feed record that are significant according to prestored criteria including subscriber interest records. Once a significant feed record is prepared, it is compared with subscriber interest records to produce an alert table. An alert transmitter transmits alerts to subscribers following the alert table. Alerts are deleted from the alert table as they are sent to subscribers. The system is suited to many types of transactional data streams, and suited for such as stock quote data streams.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: February 16, 1999
    Assignee: DataLink Systems Corp.
    Inventors: Manuel Zahariev, Nicholas R. Miller