Abstract: Passage of packets or messages is controlled between a device and a network via a virtual connection or flow which conforms to a predefined communication protocol. In connection with processing a packet or message that triggers a step in managing the virtual connection or flow, predefined authorization rules are applied to determine whether to permit the step to occur. In connection with processing a packet or message that does not trigger a step in managing the virtual connection or flow, the packet or message is permitted to pass directly via the virtual connection or flow, without applying the predefined authorization rules.

Abstract: A data processor including a data control unit having a computing portion, including a first storage unit for writing and reading a first set of data for supporting the computing portion, a second storage unit for writing and reading a second set of data for supporting the computing portion, and an arithmetic unit for calculating the first set of data read out of the first storage unit and the second set of data read out of the second storage unit and outputting result data.

Abstract: A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A pipelined processor is modified to efficiently process repeated string instructions. A repeated string instruction repeats an iteration a number of times determined by a counter variable stored in a register file. Each iteration includes at least three pipeline flows to perform a load, store, or compare of a character in the string, and to decrement the counter variable. When the last flow of an iteration reaches the execute stage near the end of the pipeline, the current value of the counter variable is compared to the maximum number of iterations which may be present in the pipeline at one time. When the counter variable is equal to the maximum number of iterations, the execute stage signals the decode stage to stop dispatching iterations. The iterations in the pipeline are completed, providing the proper number of iterations.

Abstract: A processing unit for performing convolution computation according to the HARVARD architecture which includes a first and second input register for receiving a first and second operand, a multiplier for multiplying the operand and a Arithmetic and Logic Unit (ALU) circuit. The unit further includes a coefficient storage memory which is used for loading at least one set of coefficients allowing the convolution computation. The memory storage is addressed either from an internal address generator or directly from the internal data bus thereby allowing the possibility to store either coefficients or data into the memory. The flexibility is still increased by the use of a particular set of multiplexing circuits allowing multiple configurations. An internal address generation circuit is used for performing a partial addressing of the set of coefficients thereby providing decimation capability.

Abstract: To optimize collective data movement recognition in a parallel distributed system a data movement set is formed into a data structure where access regularity is efficiently used with respect to problems, and processor expression independent of the number of processors in the parallel distributed system is introduced. By using the data structure and the processor expression, the data movement set is calculated for each dimension of an array, and the collective data movement is extracted when constructing data movement from the data movement set of each dimension.

Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated and stored into a segment register much faster than if system validation checks were also performed. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: A formula processor which computes results for a group of formulas in which at least one formula uses the result of another formula. The formula processor receives the formulas from a host and returns computed results for the formulas to the host for storage in a main memory. Formulas are received as a sequence of tokens, each token describing operands or operations. The formula processor is pipelined; as one token is interpreted and processed by the formula processor, subsequent tokens are received. The formula processor uses a computation element which is capable of performing only certain operations; before attempting each operation described by a token, the computation element determines whether the operation can be performed by the computation element--if it can be performed, it is; otherwise, the host may perform the operation itself, or rewrite the operation so the formula processor can perform it. After the formula processor computes a result for a formula, it stores this result in a cache memory.

Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated during the write back stage of the descriptor store operation, thereby eliminating processing delays typically associated with performing validation. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: A digital assistant computer device has an audio input interface and a memory adapted to receive audio input of significant time extent, and to convert the input and store it as a digital sound file. The digital assistant in one embodiment has a CPU and bus, input and display apparatus, on-board memory, and a microphone and digital signal processor for accepting and converting audio input.

Abstract: In a parallel processor device, at the time specified data is converted to parallel data by the specified unit and processed in parallel and then outputted as serial data, the data is processed and outputted in an arbitrary skipping manner without the necessity of the high speed clock signal. The first pointer mode control means 21 for controlling the address of data writing into data input register is provided, and the number and the interval of the first data when the first data is inputted to the data input register is controlled.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Abstract: A high speed instruction process system for a programmable logic controller having a first memory for storing one or more user instructions, which each instruction corresponds to a different process cycle, circuitry for processing the user instruction, a second memory for storing one or more user data, which each data corresponds to a different process cycle, circuitry for accessing a stored user data, and circuitry for processing an accessed user data in accordance with a processed user instruction, wherein the user data corresponding to a process cycle is accessed at the substantially same time as the user instruction corresponding to a different process cycle is processed.

Abstract: A signal processor includes an instruction buffer for sequentially storing information on instructions output from an instruction cache, and a first register that detects that an instruction enters in an instruction loop. When the instruction loop is formed, a control circuit controls the instruction buffer to supply the instruction in the instruction loop from its storage while placing the instruction cache in an inactive state.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in the branch-delay slot are those fetched in a period from fetching of the branch instruction till the execution of the branch instruction. Instructions are prefetched from an instruction memory into a queue memory. The queue memory includes a plurality of blocks of storage units. Instructions in the same block as a branch instruction and subsequent to the branch instruction, and instructions in the block adjacent to the block including the branch instruction provide the branch delay slot for the branch instruction. A parallel processing unit operable in a predicted branch method includes a queue memory including a plurality of entries, each of which includes an instruction and a flag indicating that an associated instruction is executed according to a prediction of a branch.

Abstract: A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero.

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Abstract: A video terminal architecture and an associated management circuit for managing the display of the video terminal are dislcosed. The terminal architecture includes a microprocessor (81) connected to the management circuit (85) via a first data bus (8549) and a first address bus (8558). The management circuit (85) manages the video display and accesses to a video memory VRAM (83). The VRAM includes the system memory and the display memory. The management circuit (85) is memory and the display memory. The management circuit (85) is also connected to a read-write character generator memory (82) via a second address data bus (8529), a second data bus (8529), and by five output lines to the video monitor.