Abstract: The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: An expandable local area hub network is provided by the present invention. The network comprises a plurality of hubs interconnected for direct communication. Each hub includes a plurality of ports for interfacing with remote stations, wherein the remote stations make requests that packets be transmitted on a memory coupled to the plurality of hubs. In use, one of the plurality of hubs is designated as a temporary controlling hub having controlling access to the memory bus to transmit packets on the memory bus. The temporary controlling hub relinquishing access to the memory bus when the temporary controlling hub has no requests to dispatch a packet on said memory bus.

Abstract: Computers are linked together to form a network. Messages are sent over the links between the computers in compressed, segmented form, the size of the segments being appropriate to the transmission characteristics of the link. A message previously received or transmitted by a computer is stored in compressed and segmented form. If it is desired to forward or re-transmit this message, the segment size of the stored form is compared against the optimum segment size for the link over which the message is to be sent. If there is a close match, then the stored segmented, compressed message is retrieved for direct transmittal, without having to resegment or recompress the message.

Abstract: An apparatus and method are disclosed for supporting a plurality of outstanding requests between a client and server in a network. If the server completes computation of a later request from a client before an earlier request, then the network protocol supports transmission of responses in an out-of-order manner to the client, thereby allowing a high degree of parallelism on the client and the server. The server buffers responses until receiving an implicit acknowledgement from the client.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: A computing system having a processor employs an accelerated virtual subsystem architecture which may reside in either the processor or chipset logic circuitry disposed on the motherboard. The accelerated virtualization process employs at least one phantom read register that provides logical status information in response to an I/O read operation or operations--avoiding engagement of the system management mode as fulfillment of the virtualization process. The at least one phantom read register is updated by the virtualization process and supplies the expected response to an application/driver program running on the processor responsive to the execution of an I/O read operation without invocation of an SMI. Preferably, at least one latch is further provided to buffer writes of indexes of index/data write pairs to further avoid engagement of the system management mode as fulfillment for the virtualization process.

Abstract: A formula processor which computes results for a group of formulas in which at least one formula uses the result of another formula. The formula processor receives the formulas from a host and returns computed results for the formulas to the host for storage in a main memory. Formulas are received as a sequence of tokens, each token describing operands or operations. The formula processor is pipelined; as one token is interpreted and processed by the formula processor, subsequent tokens are received. The formula processor uses a computation element which is capable of performing only certain operations; before attempting each operation described by a token, the computation element determines whether the operation can be performed by the computation element--if it can be performed, it is; otherwise, the host may perform the operation itself, or rewrite the operation so the formula processor can perform it. After the formula processor computes a result for a formula, it stores this result in a cache memory.

Abstract: A software architecture is provided for allowing users to impart various types of button behavior to ordinary human interpretable elements of electronic documents by associating hidden persistent character string button attributes to such elements. This architecture permits such buttons to be edited and searched through the use of the edit and search routines that are ordinarily provided by standard document editors.

Abstract: A mechanism and method for quiescing a SCSI bus by asserting the busy signal just prior to the SCSI signal pins making contact or decoupling during a hot modification. A hot modification is an insertion, removal or exchange of a device coupled to a SCSI interface bus while the system is operating (e.g., not powered down). By asserting the busy line for a predetermined and short period of time during the disturbance of the SCSI signal pins, glitches or noise introduced by the coupling or decoupling of the signal lines is isolated and prevented from causing transmission errors over the SCSI bus. According to the system described, any communication over the SCSI bus made just prior to the hot modification is allowed to complete before the signal pins are interrupted. For hot insertions, the system utilizes longer pins on the connector to assert the busy line just before coupling of the other pins of the connector.

Abstract: Apparatus for detecting move instructions in which only registers are involved. The apparatus generates signals to disable the inclusion of any SIB byte, displacement bytes and immediate bytes from the instruction length when a move instruction which only requires processor registers is encountered. The apparatus uses the generated signals for instruction length calculation and instruction prefetch pointer generation.

Abstract: A microcontroller down-loadable memory organization supporting "shadow" personality, optimized for connecting a computer system to an ISDN network to facilitate transmitting and receiving of data, the microcontroller including a processor and a memory structure having ROM memory space for storing program code therein and further including a dual port RAM for connection between the computer and the processor, the dual port RAM having RAM memory space for storing program code therein and shared RAM for storing data capable of being simultaneously accessible by the processor and the computer, wherein the program ROM and the program RAM are selectively used by the computer to store program code by the computer using a ROM/RAM* select signal, and wherein the starting address in the shared RAM wherein data is stored is selectably offset from the starting address of the code RAM and the code ROM.

Abstract: There is disclosed a method for reprogramming a 5 volt flash ROM, which includes EISA configuration code and boot code stored together in the same sector. The method of the present invention includes determining the type of flash ROM being used, and performing steps necessary to preserve the boot code while permitting reprogramming of the EISA configuration code. The method of the present invention includes modifying the conventional interrupt routine (Interrupt 15) that is used to set up and configure newly added expansion boards in an EISA bus system. The modified routine monitors the interrupt functions to determine if an erase or write is requested to the EISA configuration block in flash ROM. If an erase or write is detected, specific routines are initiated to enable the CPU to enter a protected mode to perform the necessary command sequences to the 5 volt flash ROM.

Abstract: A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices.

Abstract: A computer system includes a plate for mounting in a chassis. The plate slides into the chassis and is retained therein by a snap-in connection. An interlock device is provided for interlocking the plate and chassis. The device includes a first portion having a first end engaged with the plate and a second portion connected to a second end. The second portion extends angularly relative to the first portion and is engaged with the plate. An interlock member extends from the first portion and through an opening formed in the plate for engagement with the chassis. A pinch and pull motion removes the plate from the chassis.

Abstract: Disclosed is a migration communication control device constructed to control a continuous communication between a mobile node and a node unaffected the mobile node's migration. The migration communication control device comprises a first migration control unit, a second migration control unit on the mobile node, and a third migration control unit on the partner node. The first migration control unit comprises a packet transfer unit and an address post unit. The packet transfer unit receives a packet which was destined for an outdated address of the mobile node, generates a conversion packet which holds an updated address instead of the outdated address, and then transmits the conversion packet, while an address post unit transmits an address post message which indicates the updated address to the third migration control unit. The second migration control unit comprises a migration post unit and a packet resumption unit.

Abstract: A PCMCIA card includes a support, circuit components for providing faxmodem functions with respect to the support, a housing containing at least part of the support, a retractable cord mechanism at least partly contained in the housing for connecting the electronic component with an external device for communications therewith, the retractable cord mechanism including a cord and a storage mechanism for storing at least part of the cord in the housing, and a connector coupled to the cord for connecting to the external device. Alternate embodiments use optical or radio signal coupling from the PCMCIA card and all embodiments do not require a separate telephone connector to a telephone wall jack.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.

Abstract: A dual-microprocessor module includes two microprocessors each of a kind which has two selectable modes of operation, an independent mode in which it can operate independently and a cooperative mode in which it can cooperate with another microprocessor when interconnected in a predefined way with the other microprocessor. Conductors interconnect the microprocessors in the predefined way for operation in the cooperative mode. A housing supports the microprocessors and the conductors. An array of pins are used to mount the module in a socket on a circuit board and the pins are connected to the microprocessors. A socket/circuit board combination includes a socket having an array of holes for receiving pins of a microprocessor package.