Abstract: In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.

Abstract: A processor for character strings A, B of variable length serves for the fast detection of match, mismatch and comparative difference conditions between them. The character strings, whose lengths are delimited by character string termination marks, are split into consecutive substrings with a byte count corresponding to the data path width, and processed to detect a match, a mismatch and an end-of-byte mark. Each substring is routed via operand registers (16,18) in parallel to an arithmetic unit (20), a logic unit (22) and a comparator unit (24) and simultaneously processed. The arithmetic unit (20) subtracts one substring from the other substring, the logic unit (22) compares both substrings with each other and the comparator unit (24) compares the bytes of both substrings with the contents of a marking register (26), previously set to the end-of-string mark. These operations are executed in one machine cycle.

Abstract: A match bus operation circuit is disclosed for detecting load/store conflicts created by out-of-order instruction execution in a superscalar microprocessor having first and second busses. A ratio logic compare circuit generates a match bus indicating a match or conflict between the first and second busses. A ratio logic priority circuit is coupled to the ratio logic compare circuit for receiving the match bus and generating a priority bus indicating a first match of the match bus. A ratio logic mask circuit is also coupled to the ratio logic compare circuit for receiving the match bus and generating a mask bus that flags all instructions after the first match for discarding. A ratio logic multiple hit circuit is also coupled to the ratio logic compare circuit and indicates whether more than one instruction has matched.

Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations.

Abstract: An adapter arrangement for internetworking a non-CTOS computer means with a network of CTOS terminals, including a system-bus, this arrangement being adapted for introduction into, and cooperation with, the non-CTOS computer and comprising CTOS-net bus means for transferring signals from the system-bus plus a communication control stage for controlling and transferring signals to/from the CTOS network and a net-interface stage.

Abstract: An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive to a compare-and-branch instruction for efficient execution. The instruction sequencer detects a compare-and-branch instruction and executes it as a regular compare instruction. On the next cycle the instruction sequencer translates the instruction into a branch instruction and provides the translated instruction for execution by one of the execution units. The branch is executed, either taken or not taken, and normal program flow continues.

Abstract: An architecture is described for a single chip microcontroller wherein the microcode stored in the microcontroller's program memory may be easily modified without refabrication or removal of the microcontroller from its target environment. This is made possible by the utilization of a RAM based architecture for program memory instead of the traditional ROM based architecture.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Abstract: A monitoring computer (115) monitors a communication resource within a wireless communication system for transmissions by a communication unit. Upon detecting the transmission, which contains a unit identifier, the monitoring computer compares the unit identifier with stored system access information for the communication unit. When the unit identifier is not compatible with the stored system access information, the monitoring computer reprograms at least a portion of the system access information of the communication unit. In this manner, discrepancies in communication unit programming may be corrected.

Abstract: An output apparatus and method controls a combination of a plurality of font data stores and a plurality of conversion methods for converting font data to dot pattern data in accordance with a condition of a using right of a print data processing unit and a bit map pattern producing unit.

Abstract: A method and system to ensure the confidentiality of a local area network when a first terminal of the local area network sends out a first and second plurality of voice messages which, respectively, may and may not be received by a second terminal, consists of providing a signature distributed over the first plurality of voice messages with a portion of the signature substituted for the least significant bit of the first plurality of voice messages. Filtering is provided in the second terminal which extracts the signature from the first plurality of voice messages arriving at the second terminal and which recognizes the signature. The filtering disconnects the second terminal from the network, for a given period of time, if the predetermined message has not been recognized. The method and system to ensure the confidentiality of a local area network is suited for integrated services digital networks (ISDN) applications.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A pipelined processor includes a main memory, an instruction cache, a BTB, and a BTB registration discriminator for decoding instructions line fetched from the main memory at the time of mishit of the instruction cache and for registering branch information in the BTB when the instruction is a branch instruction. Since the branch information is already stored in the BTB even at the first execution time of the branch instruction, a branch prediction hit ratio is improved.

Abstract: An audio power management system for a computer to eliminate noise signals associated with the power-down and power-up operations of the computer during power management operations is disclosed. The audio power management system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power is applied to the amplifier. This control is done from a single digital output.

Abstract: A network connecting apparatus of this invention relates to a network connecting apparatus for connecting a plurality of networks to each other, including a plurality of network controllers, and a switch unit. A plurality of network controllers are respectively connected to the plurality of networks, each of which transmits and receives data between the network connected to itself and other networks. The switch unit connected to the plurality of network controllers, and has a network connection section for connecting at least two networks, and a switch control section for controlling the network connection section on the basis of connection requests from the plurality of network controllers to achieve a connection between desired networks.

Abstract: A data ordering system for use with personal computers having data pipelining capability is disclosed. The personal computer comprises a central processing unit (CPU) which issues data requests to one or more data exchange units, such as memory units or data Input/Output units. The data ordering system comprises a finite state machine (FSM) which receives inputs indicative of data requests transmitted by a central processing unit (CPU). The inputs cause the FSM to assume different output states which are indicative of the proper order of data requests. The state outputs of the FSM are used to enable or disable the transmission of data between the data exchange units and the CPU in order to insure the proper order of data responses to the issued data requests.

Abstract: A compact input/output processing IC, which reduces the CPU load, to which microcomputer 100, input/output processing IC 200, and various inputs and outputs are connected. Parallel signals are connected to a high-speed input/output buffer and serial signals are connected from communications control circuit 207 via serial communications circuit 206 to SIO 104. To achieve the proper control, data requiring high speed is handled by parallel communications. Serial communications is handled by shift registers, first bit of each being connected to the last bit of the other, to form a loop, with instruction and input/output data from the CPU exchanged simultaneously, thereby achieving efficient processing. This achieves better organization of the communications for input/output processing, enabling both better control and a compact hardware design.

Abstract: A rate based, end to end flow control system is disclosed for a communications network. The disclosed rate based flow control system includes each source end station selecting its transmission rate from a set of permitted discrete transmission rates. The set of permitted discrete transmission rates is based on a logarithmic encoding. The disclosed rate based traffic control system further requires each source end station to send one end to end control cell every time period T. The time period T is also known by switches in the communications network, and is used to periodically calculate an available allocation (or "fair share") of bandwidth at a switch for a given virtual circuit.

Abstract: A card contains an IC chip having a CPU, a memory, etc. When the card is inserted into a terminal device, it is connected to a host computer. Under this condition, the data in the memory of the IC card is processed by the host computer. The memory is manufactured in such a way that the memory area is segmented into a plurality of zones. An access controller for the memory is provided in the IC chip. In issuing the card, the access condition of each zone (for example, an assortment of access people and/or a type of access terminal) is programmed into the access controller by a card issuer.

Abstract: A reconfigurable, associative network apparatus and method. During a configuration phase of the associative network apparatus, active signals corresponding to wanted input patterns are configured as an associative network and distinguished from signals corresponding to unwanted input patterns; wanted input patterns can be further associated with output patterns corresponding to wanted responses. During an operational phase of a previously configured associative network, input patterns are formed from signals produced by one or a plurality of activated inputs. Selected input patterns are then filtered from a set of possible input patterns, and output patterns are obtained in response to a particular set of connections between input and output signals.