Abstract: A microprocessor includes a processor element, a memory interface element, an IO interface element, a debug support element and an internal bus interconnecting all above elements. For easy debugging, it also includes attached to the internal bus a registered boundary scan standard (JTAG) interface that accesses one or more scan chains inside the microprocessor, and is arranged for controlling DMA-type exchanges via the internal bus with other elements connected to this bus.

Abstract: A memory system contains one or more active storage elements. Each active storage element includes a memory element and a processing element associated with the memory element. The memory element contains microcode for implementing a specific function. A first bus connects the processing element to a host processor. A second bus connects the processing element to a peripheral.

Abstract: The present invention is a method for automatically correlating the logical name of devices in a local area network with the hub port used for communication by the named resource. Data for correlation is gathered from three sources. First, logical names and node identification for devices connected to the network is obtained from the resource definition file. Secondly, the frames transmitted over the network are monitored at node identification data and adapter addresses is extracted from those frames. Third, hub port identification data and adapter addresses are obtained from intelligent hubs in the network. The data from these sources is then correlated. The resource name is correlated with the adapter address by matching node identification data from the resource definition file with the node identification data captured from the transmitted frames.

Abstract: A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal processing element (PPE), a memory controller, and a multiplexor. The PPE executes a series of program instructions including local storage memory access instructions that cause the PPE to produce a local storage memory access request for accessing information within the local storage memory. The memory controller is connected to the PPE and a plurality of information resources of the parallel processing computer.

Abstract: A method and apparatus for generating an interactive component data stream, representing an application program, for an audio video interactive (AVI) composite signal, is disclosed. The method comprises the following steps. First, program files representing the application program are generated. Then, flow data defining the data structure of the interactive component is generated. Finally the data stream is generated by selectively inserting program files into the data stream in response to the flow data. Apparatus for generating such an interactive component data stream comprises a source of program files representing the application program and a source of flow data defining the data structure of the interactive component. A flow builder selectively inserts files from the source of files into the interactive component in response to data from the flow data source.

Abstract: A computer controlled apparatus includes a program counter for manifesting program count values and a processor for executing a prestored program in accordance with the program count values. The apparatus includes a read only memory with a prestored program that is accessible in response to generation of a span of program count values. Auxiliary memory includes a prestored program segment. A control circuit is coupled to the program counter and stores a predetermined program count value within the span of program count values in ROM. The control circuit is responsive to a match of a program count value from the program counter and the determined program count value to cause the program counter to be loaded with a branch program count value. That value enables the processor to immediately access and execute the prestored program segment from the auxiliary memory in lieu of a subspan of program count addresses in the ROM.

Abstract: In a highspeed and large-capacity data transfer operation effected between an extended storage unit and an input/output unit, such a data transfer system is provided, capable of preventing a performance deterioration caused by a lack of main storage capacity with employing a buffer having a large memory capacity, and deterioration of a transfer throughput caused by an overhead of an input/output operation due to a use of a buffer having a small memory capacity. There are provided a CCW for directly designating the extended storage unit as an object of a data transfer operation, and a signal line for initiating from a channel the data transfer operation between HSA-extended storage unit. Furthermore, buffers having the planes and with a small memory capacity are prepared on the HSA.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Abstract: A data processor decoding and executing a train of instructions of variable length. The data processor includes a first instruction control means for temporarily storing a prefetched instruction code and sequentially outputting said instruction code with units of a predetermined number of bits, and a second instruction control means for decoding an instruction code fed from the first instruction control means, generating control information for data processing based on the decoding, and outputting data indicating instruction update demand quantity to the first instruction control means. Based on the data indicating the update demand quantity, the first instruction control means judges whether it has output a valid instruction code of length exceeding the update demand quantity, and provides an indication of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement.

Abstract: An information processing system having a memory for storing a plurality of programs executed in a parallel processing manner, an instruction interpretation section for interpreting instructions in the programs, and an instruction execution section for executing the interpreted instructions. Queues for registering the numbers of the steps of the programs to be executed, wherein the numbers of the steps to be executed next are registered in the queues, the number of each step registered in the queues is read out, the processing to be performed in accordance with the step corresponding to the step number read out is interpreted, and instructions are given to the instruction interpretation section according to the content of the step interpreted. The step numbers of other steps to be executed are registered in the queues, and the plurality of programs are executed in parallel based on the order of the queues.

Abstract: An apparatus and method for preprocessing multimedia presentations to be delivered to customers such that delays due to interactive response time is virtually eliminated is described. The preprocessor receives as inputs an original multimedia presentation and parameters characterizing other system components, which parameters include the round trip latency between a delivery processor and a presentation processor, and generates a preprocessed multimedia presentation including a delivery schedule in the form of a labelled, directed graph.

Abstract: An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.

Abstract: In a parallel data processing system, very long instruction words (VLIW) define operations able to be executed in parallel. The VLIWs corresponding to plural threads of computation are made available to the processing system simultaneously. Each processing unit pipeline includes a synchronizer stage for selecting one of the plural threads of computation for execution in that unit. The synchronizers allow the plural units to select operations from different thread instruction words such that execution of VLIWs is interleaved across the plural units. The processors are grouped in clusters of processors which share register files. Cluster outputs may be stored directly in register files of other clusters through a cluster switch.

Abstract: An architecture for on-line reconfiguration on a RAID level 0, 1, 2, 3, 4 or 5 disk array. This architecture allows the computer system to perform reconfiguration of the disk array transparently, with disk I/O operations being performed concurrently with reconfiguration operations. The reconfiguration process allocates computer system resources necessary to support both the old and new array configurations during the reconfiguration process. Logical areas within the array are sequentially reconfigured from the old configuration to the new configuration. Data in each logical area is read from the area undergoing reconfiguration and thereafter overwritten in accordance with the new array configuration. System I/O requests received during reconfiguration which are directed to unreconfigured areas in the disk array are executed in accordance with the old array configuration.

Abstract: A computer system has a central processing unit and a functional memory coupled to the central processing unit's memory access circuitry. The functional memory includes random access memory circuitry connected in parallel with field programmable gate array circuitry. The field programmable gate array circuitry receives configuration data from the central processing unit. The configuration data defines what memory addresses the field programmable gate array circuitry will be responsive to and what computational functions the field programmable gate array circuitry will perform. The field programmable gate array circuitry includes input registers for storing data received from the central processing unit when the central processing unit's memory access circuitry asserts a first set of memory addresses defined by the configuration data and result output circuitry for communicating the results computed by the field programmable gate array circuitry.

Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.

Abstract: Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.

Abstract: In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.

Abstract: A technique for verifying a pre-recorded header in a disk drive uses verification history to protect against errors that can cause verification failure. A head number, sector address, and upper track address (track MSB) are read from the disk and compared with corresponding expected values. The results of the 5 most recent comparisons are saved in three 5-bit memories. During each verification, a programmable selection and comparison circuit selects M of the stored indicators and determines whether at least N of them indicate a match. If so, the corresponding field is declared to be correctly verified, so that subsequent reads or writes to data blocks within the corresponding sector are allowed to proceed.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.