Abstract: A computer system (6) includes a printed circuit board (302), a microprocessor chip (102), a peripheral unit chip (110), a card interface chip (112), and a display controller chip (114) mounted on the printed circuit board (302) at vertices of a quadrilateral (303). A clock buffer chip (180) is mounted on the printed circuit board (302) in the interior of the quadrilateral (303) and connected to each of the microprocessor chip (102), peripheral unit chip (110), card interface chip (112), and display controller chip (114). Other circuits, systems, and methods are disclosed.

Abstract: An apparatus and method for connecting a plurality of LAN workstations to the internet via an on-line server/interface that does not require a PC operating system dedicated to the server. The server operates in TCP/IP protocol for communication over the Internet. Only a single connection to the Internet is required in order to permit the entire LAN to operate simultaneously on the Internet. Specifically, only a single phone line is required to simultaneously serve all LAN workstations. The system is equally well suited to connect via a telephone line connection to an Internet providers's slip or PPP or via an Ethernet connection to a router or direct connection by any available means. The system does not disturb the native LAN protocol, while communicating via the internet protocol such as, by way of example, TCP/IP. The LAN is provided with a complete internet protocol service, supporting functions not generally available in the dedicated stacks previously provided for individual PCs.

Abstract: The circular queue invention herein provides a mechanism and method for producers of fixed-size data items to deliver those items to consumers even under circumstances in which multiple producers and multiple consumers share the same queue. Any producer or consumer can be permitted to preempt any producer or consumer at any time without interfering with the correctness of the queue.

Abstract: A circuit for selecting a select line from a plurality of first and second select lines is described. Each of an array of integrated circuit (IC) packages is coupled to (1) one of the first select lines and (2) at least one of the second select lines. The circuit includes a decoder for decoding a select data to select the select line, and circuitry for modifying the select data before the select data is applied to the decoder when each of the second select lines is not coupled to an IC device within each of the IC packages to ensure that the select line is not one of the second select lines. When each of the first and second select lines is coupled to an IC device within each of the IC packages, the circuitry for modifying does not modify the select data. A method for selecting a selected IC device within a selected IC package of an array of IC packages is also described.

Abstract: A bi-directional data pipeline for interfacing a memory with a communications port includes a series of four pipeline elements comprising two DMA buffers and first and second holding registers. A data word is transferred from memory to the DMA buffers, each holding one data byte of the data word. With each clock cycle, the data bytes are successively transferred through the two holding registers. Two comparators are used to determine if three successive identical data bytes are present in the pipeline. If three identical bytes are detected, run length encoding is enabled, and a run length count register is incremented for each successive identical byte received through the pipeline. The run length count and associated data byte are transferred to a FIFO for transmission over the data path. A tag associated with the run length count distinguishes the run length count from data bytes in the FIFO.

Abstract: The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.

Abstract: A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data.

Abstract: A client computer system and associated method in a computer network over which are provided programs with methods. The client computer is capable of executing the programs with reduced run-time memory space requirements. Specifically, a network communications interface receives the methods of the programs and a network communications manager loads uncompressed in available space in the run-time memory the methods when they are received. An execution controller controls execution of the programs so that the methods are invoked and not invoked at various times during execution of the programs. A compressor compresses in the memory compressible ones of the uncompressed methods that are not invoked so that space is made available in the run-time memory. The compressor also decompresses in available space in the run-time memory decompressible ones of the methods so that they may be invoked.

Abstract: A system and method for distributing data to multiple computer locations associated with a computer network determines which of the multiple network computer locations are to receive a data distribution, and then generates a first message indicating the data comprising the data distribution and the network computer locations intended to receive the data distribution. The first message and the data distribution are transmitted to the network such that each of the multiple network locations is capable of receiving the data distribution. The multiple network computer locations examine the first message so that each network computer location can determine whether it is an intended location for receiving the data distribution. Then, one or more intended network locations receive the data distribution.

Abstract: A transceiver as provided for effectively multiplexing IDE address and data lines with selected ISA address and data lines. Compatibility among the IDE data transfers and ISA functions are achieved by multiplexing the ISA lines that do not involve the ISA refresh of the ISA expanded memory. The transceiver includes an enable input that, when disabled, effectively isolates the IDE data lines from the ISA bus so that IDE data transfers can occur. When the enable input is active, the ISA lines not related to refresh are connected to the IDE data lines so that ISA operations can occur. Furthermore, a directional input is included in the transceiver for allowing a central processing unit to control the ISA when the directional input is active and for allowing a PCI/ISA bridge between the PCI bus and the ISA bus to control the ISA operations included the multiplexing. The result is a rearrangement of the IDE data lines with the ISA bus to eliminate a multitude of pins and connectors.

Abstract: A method is described for network optimization based on a multirate, circuit-switched analysis. Network loss probabilities are determined as a solution of a set of fixed point equations and the sensitivity of network performance, as a function of offered load and loss probabilities, is determined as a solution to a set of linear equations. Because the numerical complexity of solving both the fixed point equations and the sensitivity equations is of an order which renders an exact solution computationally intractable, an asymptotic approximation is applied which yields a solution to the network loss probabilities and network sensitivities. A global optimization procedure is then applied using an iterative, steepest ascent optimization procedure to yield a set of virtual path routings and capacity allocations.

Abstract: A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals.

Abstract: Delay times are modified in Ethernet network devices by adding a slot time to the minimum interpacket gap (IPG) interval between uninterrupted consecutive transmissions by a network station. If a network station transmits a data packet and has another data packet to send, modified delay time prevents the station from contending for access of the media, enabling other stations having data to transmit to attempt access on the media. If a collision occurs during the transmission of a second successive data packet, the network station uses a modified collision arbitration and automatically sets the collision delay interval to zero for the first access attempt. If another collision occurs during the access attempt, the collision interval is calculated according to the truncated binary exponential backoff algorithm.

Abstract: A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles used to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.

Abstract: A method for managing a memory address space in a memory system, the memory system having multiple block address translation entries, each entry defining a portion of the memory address space, including the steps of determining that a received virtual address references a portion of the memory address space not defined by any of the block address translation entries, reallocating at least one of the block address translation entries to define a portion of the memory address space including the received virtual address, and providing a physical address matching the virtual address by using the reallocated block address translation entries.

Abstract: A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. This level of capability is provided by only information in the I/O command blocks within the chain. A method for specifying concurrent execution of a string of I/O command blocks stored in a memory using only information in the string of I/O command blocks allows concurrent execution of a plurality of I/O commands. The method first configures one I/O command block in the string as a head of string concurrent I/O command block. Another I/O command block in the string is configured as an end of string concurrent I/O command block. The remaining I/O command blocks, i.e.

Abstract: A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2.times.2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4.times.4 block grouping to be scalable.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A computer system which provides for slowing the effective speed of a microprocessor. The microprocessor includes a disabling input that when deactivated disables operations of the microprocessor on the processor bus. A computer system according to the invention periodically deasserts this signal with the certain duty cycle, allowing the microprocessor to continue to perform necessary functions at an effective rate compatible with older microprocessors, but never requiring an actual clock frequency change. This periodic deassertion is performed in response to a memory refresh counter that periodically counts down to zero and is reloaded. By comparing an input/output register with the refresh counter, and by adjusting the input/output register, the deasserting signal to the processor is periodically deasserted with a selectable duty cycle.