Abstract: A moderately coupled floating point and integer units of a processor allows for rapid transfer of data between the two units. The integer unit is comprised of a plurality of integer registers arranged into an integer register file and coupled to one or more integer execution units. Similarly, the floating point unit is comprised of a plurality of floating point registers arranged into a floating point register file and coupled to one or more floating point execution units. The two units operate as separate units except for the data transfer between them on a transfer bus. The transfer bus is the only direct data link between the two register files. Multiplexers are used to control the bit transfer between the two register files so that all or some of the bits of a register are transferred to a receiving register. Furthermore, the data transfer scheme allows for both numeric and Booleans to be transferred and compounding of Booleans can be performed in either numeric unit.

Abstract: Service requests from client objects in a computer network are processed in accordance with the desirability of use of the transport network available for communication with the server objects so that local platform servers are used whenever possible to avoid data marshalling and unmarshalling. A local memory queue is used to hold the service request for interrogation by the local server. Local memory storage may be used to hold data or other portions of the service request so that only minimal data need be processed by the memory queue.

Abstract: A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

Abstract: Parameters representing types of machines to be connected to a network, connection types thereof to the network, and operation modes thereof in the network system are set from an information processing apparatus. The obtained parameters are written as parameter files on a recording medium. In each network machine, a network system is automatically constructed by referencing the files. Consequently, the parameter setting operations for the installation of the machine are simplified and there is achieved automation of operations in each network machine.

Abstract: In an information processing apparatus with a main control unit and a printer, a transfer unit transfers commands and data between the main control unit and the printer, a memory temporarily stores the data transferred to the printer, and a detector detects the remaining capacity of the memory. The information on remaining capacity of the memory is supplied to the main control unit to improve the execution efficiency of the main control unit.

Abstract: A circuit to control a network interface includes a first interface circuit and a second interface circuit. The first interface circuit is capable of negotiating one protocol to use from a plurality of known interface protocols. The first interface circuit controls the network interface when the negotiated interface protocol is supported by the first interface circuit. Otherwise, if the second interface circuit supports the negotiated protocol, the first interface circuit releases control of the network interface to the second interface circuit. The first interface circuit takes control of the network interface from the second interface circuit when the second interface circuit signals the first interface circuit that reliable communication with the network has been lost.

Abstract: A parallel processor array with a two-dimensional crossbar switch architecture. Individual processing elements are configured as clusters of processors, wherein the individual processing elements within each cluster are interconnected by a two dimensional cluster network of crossbar switch elements. The clusters are interconnected via a two dimensional array network of crossbar switch elements, supporting high-bandwidth inter-processor data shuffles that characterize parallel implementations of sensor processing problems. Input data is supplied directly into the array network of crossbar switch elements, which allows an optimal initial partitioning of the data set among the processing elements. The array architecture supports a virtual array sizing, where the processor array can be treated as a variable sized array with dimensions that are software controllable, selectable to match system characteristics.

Abstract: In the processing and transmission of an image, there is generated additional information relative to the transmitting apparatus or to the image signal to be transmitted, then an image signal representing an input binary image and an iamge relative to the additional information is binary encoded, or an input multi-value image signal is multi-value encoded, and the binary encoded image signal and the multi-value encoded image signal added with data relative to the additional information are selectively released.

Abstract: A configuration manager for configuring a network device remotely coupled thereto and an associated computer-implemented method for configuring the network device. The configuration manager includes a configuration script stored in a memory subsystem of a computer system and first and second software modules respectively executable by a processor subsystem of the computer system. The configuration script contains a series of executable instructions for constructing a configuration file and a bootptab file for a first specified type of network device. By executing the instructions contained in the configuration script, the first software module may construct a configuration file suitable for upload to a network device and a bootptab file suitable for identifying the network device.

Abstract: Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Hierarchical scan logic supplies the relative age indications of loads with respect to stores (and of stores with respect to loads).

Abstract: A digital computer system having a socket capable of accepting any one of a family of processors, the family being defined as those processors having commonality of their respective basic input/output system code. Each processor has assigned pins for conducting specified signals, the pins engaging the socket. There is dissimilarity between at least two of the processors of correspondence where at least one of the specified signals, of one of the processors, is assigned to a different pin from the other processors. When such dissimilarity is present, the signal is redirected to the appropriate designated pin for the particular type of processor.

Abstract: A structural key is checked under program control to control the mode of operation for a processor-based electronic circuit board. A break-away key portion of the circuit board is connected to the main portion along a boundary of frangible links with circuit paths traversing the boundary and carrying logic signals. The presence or absence of the break-away portion is sensed by sensing the bit pattern at an I/O address. If the absence of the break-away portion is sensed, the function of a user-commanded motion block is tested and processor operation is limited to executing functions for the mode corresponding to the absence of the break-away portion.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/scattering system includes: one processor having a buffer for temporarily storing data gathered from or transmitted to other processors, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system; each of the other processors having a buffer for temporarily storing data to be transferred or data to be received, a transfer control unit for controlling data transmissions from the buffer to the common bus, a reception control unit for selecting the reception data from among all data on the common bus, a three-state buffer for transmitting data from the buffer to the common bus, and a switching un

Abstract: A computer system having a scaleable software architecture is disclosed. The scaleable communication or data replication architecture that enables transparent replication of data or state information over a network of geographically dispersed processing units. Transparent data replication over a geographically dispersed computer network is useful in applications such as parallel computing and disaster recovery. The communication architecture also provides a transparent interface to a kernel I/O subsystem, device drivers and system applications. The communication architecture provides a distributed data model presenting a single system image of the I/O subsystem that allows two or more geographically dispersed processing units or clusters thereof, access to common data. In one particular implementation, the communication architecture permits RAID algorithms, such as RAID level 1 and RAID level 5 state information to be applied to the geographically dispersed network for site disaster recovery.

Abstract: In a parallel data processing control system for a parallel computer system having a plurality of computers and an adapter device connecting the computers to each other, a first unit, which is provided in the adapter device, transfers pieces of data processing progress state information to the computers. The pieces of the data processing progress state information respectively indicate data processing progress states of the computers. A second unit, which is provided in each of the computers, holds the pieces of the data processing progress state information. A third unit, which is provided in each of the computers, holds management information indicating a group of computers which share a data process. A fourth unit, which is provided in each of the computers, determines whether or not the computers in the group have completed the data process on the basis of the pieces of the data processing progress state information and the management information.

Abstract: Remote procedure call (RPC) objects are provided in both a client node and a server node of a client-server network for invoking and responding to service requests generated by calls to local service objects. Specifically, the RPC objects comprise a "caller" object which, once instantiated, accepts service requests from client objects. A service request made by calling a function in the local service object is automatically routed by the caller object to a local service program if the requests can be serviced locally, or to a remote server node if the appropriate service program is located on the remote node. The RPC objects also include a "dispatcher" object which is located at the remote service node and receives incoming service requests. The service requests are actually satisfied by means of service functions which are part of service objects in the server node, but these latter service functions are associated with the local service objects by means of a "dictionary" located in the dispatcher object.

Abstract: A data processor intended for a single instruction, multiple data mode operation includes memory that is external to the processor array, and a controller that dynamically and selectably interconnects multiple edges of the processor array with the memory and with I/O ports. A separate controller module is provided for each memory channel, and interconnects with corresponding edge processing elements of the processor array. The controller modules for the different channels are independent of each other, as are the channel memories. In the case of a rectangular processor array, each channel memory can be implemented with only three memory stores that are interconnected with the four edges of the processing array and the I/O ports through the channel controller module, yet for most algorithms provide a throughput that is comparable to that resulting from the use of four memory stores.

Abstract: A system and method for distributing video or audio or other interactive program information to multiple users includes master files of such program information that can be selectively distributed to community systems in which individual users are selectively coupled with computing microcells that process the selected program information from within the entire set of programs that are all contained in moving memory modules which cyclically and recurringly distribute the entire set of programs to multiple computing microcells. A microcell access switch controls coupling of users to computing microcells, and controls selective interaction between master files and moving memory modules for updating the set of programs stored therein. The microcell access switch provides network programs to users without requiring a computing microcell for enhanced versatility and reduced system costs.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.