Abstract: A bi-directional vector rotator that can be used to provide outputs having phases that are rotated in clockwise and counter clockwise directions relative to that of the input signal. The bi-directional vector rotator includes a product term generator that receives a complex input and a complex carrier signal and generates product terms. Combiners then selectively combine the product terms to generate the outputs. By sharing the same product term generator for both clockwise and counter clockwise phase rotations, the bi-directional vector rotator can be implemented using less circuitry than that for a conventional design employing two uni-directional vector rotators. Moreover, only one complex carrier signal is needed by the bi-directional vector rotator instead of two for the conventional design. Further simplification in the design of the bi-directional vector rotator can be achieved by selecting the proper sampling rate for the complex input.

Abstract: The present invention discloses a linearisation and modulation device for a power amplifier.

Abstract: A complex signal correlator such as can be implemented in a correlation detector system affords a unique algorithm which estimates the codifference correlation between two complex signals based on the sum and difference of codifference estimates, each codifference estimate having equivalently associated therewith a dispersion estimate. Typical embodiments provide a receiving antenna and a receiver inclusive of the codifference correlator, wherein radio frequency waves are down converted and sampled, the sampled signals are correlated with a reference signal contained in a memory, and the resultant correlation signal is detected and transduced. The inventive correlator is based on an alpha-stable distribution and, in comparison with conventional alpha-stable distribution-based correlators, can more effectively operate in a realm wherein alpha is less than one.

Abstract: A digital variable-frequency oscillator has an output frequency thereof variable in dependence upon a frequency control variable. Externally input data are stored in a data storage device, from which the data are generated in accordance with the output of the digital variable-frequency oscillator. A remaining data amount of the data storage device is detected in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal. A filtering operation is performed on values of the frequency control variable so as to calculate an average value of the frequency control variable. A new value of the frequency control variable is calculated based on the calculated average value and the difference between the detected remaining data amount of the data storage device and a target data amount thereof.

Abstract: A memory-efficient trellis coded quantizer divides consecutive trellis columns into groups or windows each containing the maximum number of columns for which each pair of columns in a window still retains statistical dependence with respect to the states of the column and in relation to any trellis path connecting the two columns. Back searching for code words operates on each individual window, rather than on the overall trellis. Windows are sequentially processed in pairs to derive the code words for the input that has been trellis coded. Required storage is reduced, since trellis and code word storage is required only for the windows currently being processed.

Abstract: A digital communication system is presented implementing a data transmission method which allows each of a pair of communication devices coupled to a transmission line to both transmit and receive data during each cycle of a clock signal (i.e., simultaneous bidirectional data transmission). The digital communication system includes a first and second communication devices coupled to opposite ends of a transmission line. Both the first and second communication devices operate in response to a periodic clock signal. The first and second communication devices simultaneously: (i) drive an output data signal upon the transmission line during a first portion of a period of the clock signal, and (ii) receive an input signal from the transmission line during a remainder of the period of the clock signal. The communication devices may be coupled to receive the clock signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.

Abstract: A method (10) is provided of setting up a call over a multiple bit-rate transmission channel between a central module (25) and a remote module (22). The channel comprises at least one first transmission channel (401) having a primary bit rate and at least one second transmission channel (402) having a secondary bit rate. Each of said first and second transmission channels is a two-way channel comprising a first transmission half-channel (43, 45) in one direction and a second transmission half-channel (44, 48) in another direction. The method comprises the following steps: setting up a call on the primary transmission channel, scanning for a signal indicating a secondary bit-rate requirement, and if a signal indicating a secondary bit rate requirement is detected, bit-rate switching from said first transmission channel (401) to the second transmission channel (402).

Abstract: There is provided an apparatus for and a method of measuring a jitter wherein a clock waveform XC(t) is transformed into an analytic signal using Hilbert transform and a varying term &Dgr;&phgr;(t) of an instantaneous phase of this analytic signal is estimated.

Abstract: A signal source generates a phase-modulated output signal responsive to a phase-modulation signal. A phase splitter splits the phase-modulated output signal into two or more phase-offset output signals. A switch provides a selected one of the phase-offset output signals from the phase splitter to a transmit amplifier circuit. Large phase transitions in the phase-modulation signal are detected and reduced to decrease modulation bandwidth requirements at the signal source. When a phase transition in the phase-modulation signal is reduced, the switch is coherently switched from one phase-offset output signal to another to substantially restore the full phase transition in the output signal presented to the transmit amplifier circuit. In this manner, the transmit amplifier receives substantially the same phase transitions as are in the original phase-modulation signal.

Abstract: The present invention concerns a new type of rake receiver, namely, a multimode rake receiver, which may be included within either a mobile station or a base station, and which has dynamic pilot signal searching and multipath reception and combining capability, for CDMA, cdma2000, W-CDMA, or other mobile communication systems. The adaptive, multimode rake receiver includes a network interface, a plurality of adaptive multimode rake fingers, and a multimode processor. Each adaptive multimode rake finger and the multimode processor are responsive to first configuration information (a first mode signal) to configure for a path reception functional mode and are further responsive to second configuration information (a second mode signal) to configure for a searcher functional mode, providing the multimode rake receiver with acquisition, traffic, and idle modes.

Abstract: A bit synchronization device which extracts an output data signal and an output clock signal from an input data signal on the basis of a multi-phase clock signal. The bit synchronization device is provided with a processing circuit which holds a phase corresponding to a change point of an input data signal with a multi-phase clock signal, and while the input data has a phase without change point, carrying out a data identification free from an error by selecting a clock signal corresponds to the phase without change point.

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.

Abstract: An angle demodulator in which an FM modulated wave is converted into an IF signal (SI) in the form of digital so as the signal is supplied to a Hilbert transformer (81) and to an outer product calculation section (82). The Hilbert transformer (81) allows the phase of the IF signal (SI) to shift ninety degrees and supplied it to the outer product calculation section (82). An integrator (84) calculates a phase of a cosine wave of an angular frequency that a frequency control unit (83) designates. A phase converter (85) calculates the cosine wave and an instantaneous value of a signal in which the cosine wave shifts ninety degrees out of phase so as to supply the value to the outer product calculation section (82). The outer product calculation section (82) supplies to the frequency control unit (83) an outer product of a vector including a value of the IF signal and of a signal from the Hilbert transformer (81) and a vector including a value supplied from the phase converter (85).

Abstract: A method and apparatus for frequency domain equalization. The method and apparatus are particularly well suited for use in a receiver in a multicarrier transmission system that has predetermined symbols periodically embedded in the transmissions, such as in an ADSL system. The equalizer apparatus includes a digital filter having a plurality of single-tap filters. The filters operate on the symbols in the frequency domain, accepting frequency domain representations of the received symbols. The equalizer also includes a reference symbol generator that provides reference symbols, a coefficient generator that accepts the equalized frequency domain symbols from the digital filter and the reference symbols and updates the filter taps using a received predetermined symbol and the reference symbol. The coefficient generator includes a generator filter having a first and a second adaptation increment, an error generator, and a threshold detector that controls the coefficient generator in response to said error signal.

Abstract: Signal points from a PCM-derived constellation are selected for transmission via a modulation technique which employs different levels of redundancy coding—including the possibility of no redundancy coding—for respective different sub-constellations of the overall PCM-derived constellation. The coding that is employed for at least one of the sub-constellations is carried out independently from any coding that is employed for any of the other sub-constellations. The PCM-derived constellation and the overall modulation technique are designed so as to accommodate the possibility that the telecommunications system in which the modulation technique is implemented may include so-called bit robbing and so-called digital attenuation.

Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.

Abstract: A pilot symbol detection section detects and extracts pilot symbols from a despread signal. An inter-symbol phase shift detection section detects the phase shifts between adjacent pilot symbols in a pilot symbol block (inter-symbol phase shifts). An inter-pilot block phase shift detection section detects the phase shifts between adjacent pilot symbol blocks (inter-pilot block phase shift). An inter-symbol phase shift averaging section takes the average of the inter-symbol phase shifts. An inter-pilot block phase shift averaging section takes the average of the inter-pilot block phase shifts. A frequency correction determination section determines an appropriate frequency correction based on the outputs of the inter-symbol phase shift averaging section and the inter-pilot block phase shift averaging section.

Abstract: In all wireless systems, the first operation that must take place at the receiver is the acquisition of the carrier and timing. OFDM systems are particularly sensitive to carrier offsets since these can introduce inter-carrier interference and loss of signal power. An algorithm, termed modulo-sub-carrier (ModSC), which can estimate the local oscillator offset in a fast and efficient manner has been devised. The carrier offset can be brought to within one half the carrier spacing within 1 to 10 OFDM symbols. By inserting a null in the center carrier, carrier acquisition can be easily accomplished by locating this null in the FFT bins at the receiver. The offset of this null from the designed position indicates the local oscillator offset in units of number of sub-carriers. An additional carrier tracking algorithm is used to estimate the offset within one half the inter-carrier spacing. Together, the ModSC and carrier tracking algorithms completely estimate the local oscillator offset.

Abstract: In one embodiment, the present invention provides a radio frequency transmitter that may have a processor and a controller that reduce current consumption of the power amplifier of the radio frequency transmitter.

Abstract: An information processing apparatus in which an eye center measuring unit determines a code judgment point from a peak timing signal supplied from a timing signal generation circuit and an amplitude signal supplied from an interpolator and detected by an amplitude detector, and outputs it to a multiplier via an amplifier, a subtracter, and a reciprocal generating unit. A zero cross point measuring unit determines a code change point from a zero cross timing signal supplied from a timing signal generation circuit and an amplitude signal supplied from the interpolator and detected by the amplitude detector, and outputs it to the multiplier via a subtracter. The multiplier multiplies the supplied signals, and a dB converter converts a supplied signal into a signal in decibels and outputs the signal to a display circuit.