Abstract: A non-orthogonal noise detecting device for a CDMA communication system. In the device, a despreader despreads multiple channel signals including a specific channel with an orthogonal code assigned to the specific channel repeating at least two same second symbols at a given first symbol duration, to generate despread repeated symbols. A difference signal generator receives the despread second symbols, and generates a difference signal between a presently received second symbol and a previously received second symbol. A noise detector converts the difference signal to an energy value to generate a non-orthogonal noise signal.

Abstract: A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the 10 data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Abstract: Methods and apparatus for synchronization of a transmitter and a receiver are based on orthogonal sequences having optimized correlation properties. The transmitter may generate signed versions of S-Hadamard sequences that are obtained by position-wise scrambling a set of Walsh-Hadamard sequences with a special sequence having complex elements of constant magnitude. The receiver estimates a time location and sequence identity of a received version of the synchronization signal.

Abstract: A method of and apparatus for capacity determination in a telecommunications system, in the presence of Gaussian and non-Gaussian noise. The ratio of Gaussian to non-Gaussian noise is determined utilising a statistical metric. Preferably the metric is Kurtosis or the 3rd Cumulant of the Probability Density of the signal at each frequency. The determination of the ratio of Gaussian to non-Gaussian noise enables a more accurate determination of Noise, which in turn allows greater utilisation of actual available capacity in the system.

Abstract: Jitter measuring equipment includes timing recovery circuitry with a first filter having a Gaussian-family response to enable the equipment to tolerate relatively long runs of data symbols of a single value without affecting the accuracy of timing of clock recovery. Potential distortion of the jitter measurement which could arise from this amplitude response characteristic is alleviated by applying the demodulated baseband signal, prior to jitter measurement, to a demodulated filter having an amplitude response characteristic that is approximately the inverse of the response of the first filter.

Abstract: Transmitting/receiving apparatuses are installed in a base station and a mobile station, respectively, to perform mutual transmission and reception by using a plurality of spreading codes. The transmitting/receiving apparatus installed in the base station has a block for designating to the mobile station the kind and the number of spreading codes used in a reverse link from the mobile station to the base station through a forward link at the time that communication with the mobile station is started. The transmitting/receiving apparatus installed in the mobile station has a block for transmitting a signal to the base station by using spreading codes of the designated kind and number.

Abstract: An Asymmetric Digital Subscriber Loop (ADSL) Discrete Multi-Tone system has disjoint and adjacent upstream and downstream channels. During the training phase of an ADSL connection, an ADSL DMT transmitter first determines a round trip propagation delay by transmitting a ranging signal to a far-end ADSL endpoint. During the subsequent communications phase, the ADSL transmitter synchronizes transmission of DMT symbols to a reference clock. In addition, the cyclic extensions of each DMT symbol are increased as a function of the propagation delay.

Abstract: A system and method for simultaneous transmission and receival where the received signal is downconverted in a downconverting unit by using a portion of the transmitted modulated signal as LO for the downconversion. The downconversion is performed to an intermediate frequency signal having a frequency equal to the difference between the frequency of the transmitted signal and the frequency of the received signal. There is provided a common antenna for transmitting and receiving, and a duplex filter in front of the antenna to separate the transmitted signal and the received signal with the transmitter data on the transmitter side having been applied to a modulator. In front of the duplex filter on the transmitter side is provided a power amplifier. On the receiver side there is, in addition, provided a demodulator to permit withdrawal of user data for the user on the receiver side.

Abstract: A method of and device for recognizing a network-synchronous interfering signal during a data transmission in which pauses occur between useful signals, with the duration of a shortest pause being Tp and a main frequency being f are disclosed. The method includes the steps of defining a time span Td being shorter than the shortest pause Tp, but longer than the longest period 1/f or ½ f, of a network-synchronous interfering station; determining whether pauses occur that are longer than Td during a time period T check>Td; and interpreting an occurrence of pauses as the presence of a useful signal without a network-synchronous interfering signal, and interpreting a lack of an occurrence of pauses as the presence of an interfering signal.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors. Further, the current limiting mode includes a distortion adjustment circuit to limit distortion at a crossover point at which current limiting effects occur.

Abstract: A method and an apparatus for detecting data symbols of a multiple-phase-shift-keying (MPSK) modulated slot used for radio reception of digital data are disclosed. The method and apparatus simultaneously accomplish signal equalization and symbol detection. A simplified algorithm is used which is sub-optimal but closely approximates an optimal solution which significantly reduces computational load. A solution vector is constructed and data symbol values in the solution vector are perturbated. After each perturbation, a solution error is computed to determine whether the perturbated value provides a better solution. Perturbation continues until an optimal solution is found or a maximum number of iterations have been performed. The advantage is an improved, cost-effective radio receiver which enables faster wireless data transfer.

Abstract: A bandpass phase tracker automatically samples at prescribed carrier phases when digitizing a vestigial-sideband intermediate-frequency signal, which VSB I-F signal is modulated in accordance with a baseband symbol code of a prescribed symbol frequency. Heterodyning circuitry mixes oscillations from a local oscillator with the VSB I-F signal received from the I-F amplifier to generate an analog low-frequency heterodyne signal offset from zero frequency. The heterodyne signal is digitized in accordance with a first sampling clock signal to supply input signal for digital demodulation circuitry that demodulates the VSB I-F signal to supply real and imaginary components of a demodulated signal at baseband. The real component of the demodulated signal is supplied to an equalizer and symbol decoded; the imaginary component controls the frequency and phase of the local oscillator.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided that is a second order circuit. The use of a second order circuit provides improved distortion characteristics, particularly at low frequencies.

Abstract: A method and apparatus for reducing the peak power probability of a spread spectrum signal by clipping the signal to constrain its spectrum within error-shaped bounds. The method includes the steps of generating a clipping threshold signal, generating a clipping error signal responsive to both the clipping threshold signal and the spread spectrum signal, filtering the clipping error signal to produce a shaped error signal, and subtracting the shaped error signal from the spread spectrum signal.

Abstract: The pulse signal generating apparatus includes a control circuit, a shift register, a counter and a processor. The control circuit generates a trigger signal to trigger a transition of a signal level. The shift register to which level data to define a signal level is set and in which the level data is serially shifted in response to the trigger signal from the control circuit to generate a pulse signal. The pulse signal is generated based on data shifted out from the shift register. The counter increments a content according to the trigger signal from the control circuit to generate an interruption signal every time the content reaches a predetermined value. The processor sets the level data in the shift register in response to the interruption signal from the counter.

Abstract: Methods of designing successively refinable Trellis-Based Scalar-Vector quantizers (TB-SVQ) include a multi-stage process wherein a TB-SVQ is applied to a set of digital data to set up a codebook boundary and to obtain a non-uniform density gain for a constellation in which the data signals will be encoded. In at least one more stage, a Trellis coded quantizer (TCQ) is applied to the output codebook boundary of the first stage to obtain a granular or shaping gain of 1.53 dB. The inventive methods successively refine the TB-SVQ so that robust signal transmission is achieved. By applying a multi-stage process wherein a TB-SVQ is utilized in the first stage and a TCQ is utilized in the second and successive stages, the computational complexity and time for encoding the constellation are greatly reduced.

Abstract: A digital radio tuner signal estimator receives a digitized in-phase (I) data signal and a digitized quadrature (Q) data signal and provides an estimated amplitude gain signal and an estimated signal-to-noise ratio signal value. The signal estimator includes a symmetrical matched I data digital filter having a first I filter section that filters the received I data signal and provides a first I data signal, and a second I filter section that filters the I data signal and provides a second I data signal. The signal estimator also includes a symmetrical matched Q data digital filter having a first Q filter section that filters the received Q data signal and provides a first Q data signal, and a second Q filter section that filters the Q data signal and provides a second Q data signal. The first and second I data signals and the first and second Q data signals are processed to compute an estimated amplitude gain.

Abstract: This invention provides a dynamic frequency hopping system that utilizes information from multiple base stations. The system assigns frequency hopping patterns based on current interference and traffic environments to avoid interference thus gaining the benefits of interference averaging and interference avoidance. The system imposes less stringent measurement requirements on terminals (wireless mobile devices) because many measurement requirements are replaced by generating estimates based on measurement data received from other base stations within a base station neighborhood. The system may continuously verify that the frequency hopping patterns assigned to the links of the system optimizes system performance. The system compares system performance of possible frequency hopping patterns against currently assigned frequency hopping pattern to optimize system performance.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: The present invention relates to a phase-locked loop (PLL) circuit and, more particularly to a PLL with a phase lock detection circuit. The PLL circuit includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a frequency divider, and a phase lock detection circuit having two current charging/discharging circuits with first and second constant current sources for generating a phase lock signal having a pulse form through charging/discharging a capacitor. A voltage level of the capacitor is changed with a hysteresis characteristic. In the out-of-lock state of the PLL circuit, the discharging speed of the capacitor is faster than the charging speed thereof. In the phase lock state of the PLL circuit, the charging speed of the capacitor is faster than the discharging speed thereof.