Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Abstract: A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to

Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.

Abstract: A discrete fracture network model is upscaled to a simulation grid having effective permeabilities for each grid cell. Prior to computing the effective permeabilities, the grid cells are grouped in distinct grid cell clusters, such that flow via fractures is only possible between grid cells that mutually belong to the same grid cell cluster. This is achieved by grouping fractures into distinctive fracture clusters, whereby all fractures that are physically connected with each other by intersection, either directly or indirectly via a number of other physically connected fractures, exclusively belong to one fracture cluster. Each grid cell is assigned to exclusively one fracture cluster. After defining the grid cell clusters, effective permeabilities are calculated for each grid cell using only the fractures of the fracture cluster to which the grid cell is assigned while fractures from other fracture clusters are ignored. Inter-cluster flow impediment data is assigned to selected grid cells.

Abstract: The invention comprises an infrared source and method of use thereof comprising the steps of: (1) providing a solid state source comprising: an electrically conductive zinc oxide film having a thickness of less than five micrometers and a film of metal oxide particles, the metal oxide particles comprising a mean diameter of less than ten micrometers; (2) passing an alternating, pulsed current through the zinc oxide film, the pulsed current heating the zinc oxide film to greater than 700° C. in less than twenty milliseconds using less than one Watt, which results in a first infrared emission from the zinc oxide film; and (3) heating the film of metal oxide particles, using thermal conduction from the zinc oxide film, to at least 700° C., resultant in a second infrared emission from the film of oxide particles, where the first and second infrared emissions exit the source through an emission side.

Abstract: A display device includes a scan line extending primarily in a first direction, disposed on a substrate, and transmitting a scan signal, a data line extending primarily in a second direction intersecting the first direction and transmitting a data signal, a driving voltage line extending primarily in the second direction and transmitting a driving voltage, a plurality of transistors including first and second transistors, wherein the second transistor is connected to the scan line and the data line, and the first transistor is connected to the second transistor, a light emitting element connected to the plurality of transistors, and a storage capacitor disposed between the substrate and an active pattern of the first transistor, the storage capacitor including a first electrode disposed on the substrate and a second electrode at least partially overlapping the first electrode. A first insulating layer is disposed between the first and second electrodes.

Abstract: A semiconductor device of an embodiment includes a nitride semiconductor layer, a first electrode provided on the nitride semiconductor layer, a second electrode provided on the nitride semiconductor layer, a third electrode provided above the nitride semiconductor layer, the third electrode provided between the first electrode and the second electrode, the third electrode containing a polycrystalline nitride semiconductor containing a p-type impurity, and a first insulating layer provided between the nitride semiconductor layer and the third electrode.

Abstract: The subject technology is related to methods and apparatus for discretization and manufacturability analysis of computer assisted design models. In one embodiment, the subject technology implements a computer-based method for the reception of an electronic file with a digital model representative of a physical object. The computer-based method determines geometric and physical attributes from a discretized version of the digital model, a cloud point version of the digital model, and symbolic functions generated through evolutionary algorithms. A set of predictive machine learning models is utilized to infer predictions related to the manufacture process of the physical object.

Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

Abstract: A system for irrigating an irregularly shaped area including a sprinklers and an electronic device in wired or wireless communication with the sprinkler. The electronic device has a processor and a memory storing programmable instructions causing the sprinkler to irrigate watering sectors according to predefined watering parameters, such that an irregular irrigation pattern is achieved.

Abstract: Various embodiments of the present technology may comprise a method and device for a multi-branch transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. At least two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a single photosensitive element or multiple photosensitive elements. The device may comprise a multi-branch channel region defined by the area underlying a gate region and substantially surrounded by the doped regions.

Abstract: The subject technology is related to methods and apparatus for discretization and manufacturability analysis of computer assisted design models. In one embodiment, the subject technology implements a computer-based method for the reception of an electronic file with a digital model representative of a physical object. The computer-based method determines geometric and physical attributes from a discretized version of the digital model, a cloud point version of the digital model, and symbolic functions generated through evolutionary algorithms. A set of predictive machine learning models is utilized to infer predictions related to the manufacture process of the physical object.

Abstract: A method for operating a machine-human interface in an automation environment includes receiving or automatically retrieving, by a machine-human interface computer, sensor data corresponding to a plurality of humans working the automation environment. The machine-human interface computer applies a human model to the sensor data to yield a plurality of human state records, each human state record corresponding to one of the humans working within the automation environment. The machine-human interface computer also identifies automation tasks using a factory state schedule. Based on the plurality of human state records, the machine-human interface computer assigns the automation tasks to the plurality of humans.

Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract: A display device having a high aperture ratio and including a capacitor that can increase capacitance is provided. A pair of electrodes of the capacitor is formed using a light-transmitting conductive film. One of the electrodes of the capacitor is formed using a metal oxide film, and the other of the electrodes of the capacitor is formed using a light-transmitting conductive film. With such a structure, light can be emitted to the capacitor side when an organic insulating film is provided over the capacitor and a pixel electrode of a light-emitting element is formed over the organic insulating film. Thus, the capacitor can transmit light and can overlap the light-emitting element. Consequently, the aperture ratio and capacitance can be increased.

Abstract: The present disclosure provides a method of patterning a polymeric layer based on the chemical reaction of two chemical compounds. One chemical compound is provided in the polymeric layer and another chemical compound is deposited on the polymeric layer by, for example, ink-jet printing. The method allows for fabrication of, for example, metallization patterns for solar cells electronic components, integrated devices and formation of selective doped areas in solar cells amongst others.

Abstract: The subject specification comprises enhanced power system balance control for a multi-tier hierarchical electrical distribution network (EDN). The EDN comprises a specified number of distribution network node controller (DNNC) components employed to desirably control power system balance, data communications, and power distribution between respective tiers of the EDN to facilitate efficient power distribution. In each tier, a power system balance component (PSBC), associated with a DNNC component, can monitor power system balance, such as load phase balance, associated with multi-phase power distribution for its tier, and detect power system imbalances in that tier. A power balance correction action can be identified and executed (e.g., automatically) in response to the detected power system imbalance to rectify the imbalance, wherein the correction action can include dynamic switching of loads between phases and/or filtering of the power signal.

Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.