Patents Examined by Amar Movva
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Patent number: 10490554Abstract: According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view.Type: GrantFiled: February 21, 2019Date of Patent: November 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Seongho Kim
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Patent number: 10481491Abstract: A method can be used to generate a fluid droplet pattern for an imprint lithography process using a fluid dispense system having fluid dispense ports. The method can include determining a fluid droplet pattern for dispensing a formable material onto a substrate; during a first pass, dispensing the formable material onto the substrate to form a first part of the fluid droplet pattern for an imprint field; offsetting the fluid dispense ports and substrate relative to each other in an offset direction; and during a second pass, dispensing the formable material onto the substrate to form a second part of the fluid droplet pattern for the imprint field. The method can be used to form a patterned layer over a semiconductor wafer in fabricating an electronic device. An apparatus can be configured to carry out the method.Type: GrantFiled: December 12, 2016Date of Patent: November 19, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Edward Brian Fletcher, Timothy Brian Stachowiak
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Patent number: 10483277Abstract: According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. The conductive layer is provided on the interconnect portions. The stacked body is provided on the conductive layer and includes electrode layers stacked to be separated from each other, and each of the electrode layers extends in the second direction. The columnar portions are provided inside the stacked body, each of the columnar portions includes a semiconductor portion extending in a stacking direction of the electrode layers and a charge storage film provided between the semiconductor portion and the stacked body.Type: GrantFiled: March 20, 2017Date of Patent: November 19, 2019Assignee: Toshiba Memory CorporationInventor: Jun Nishimura
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Patent number: 10483355Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.Type: GrantFiled: October 24, 2017Date of Patent: November 19, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Matthias Bauer, Hans-Joachim L. Gossmann, Benjamin Colombeau
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Patent number: 10476185Abstract: A display device including a display panel including a base substrate, a plurality of pixels disposed on the base substrate, and a plurality of panel pad rows that are spaced apart from the pixels in a first direction. Each of the panel pad rows includes a plurality of panel pads arranged in a second direction crossing the first direction in a perpendicular manner, a connecting circuit board disposed on the display panel and connected to the panel pads, and a connection member disposed between the display panel and the connecting circuit board to electrically connect the display panel to the connecting circuit board. A minimum-spaced distance between an edge of the base substrate and the panel pads adjacent thereto may be optimized to improve an adhesion property and an electrical connection reliability between the panel pads and the connecting circuit board.Type: GrantFiled: January 21, 2019Date of Patent: November 12, 2019Assignee: Samsung Display Co., Ltd.Inventors: Myungchul Kim, Nam-sik Ko, Sedae Ki, Moonju Kim, Sangkueon Lee, Seunghoon Han
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Patent number: 10468247Abstract: A method can be used to generate a fluid droplet pattern for an imprint lithography process using a fluid dispense system having fluid dispense ports. The method can include determining a first fluid droplet pattern for the formable material dispensed at a preset minimum pitch or an integer multiple thereof; determining a second fluid droplet pattern based on the first fluid droplet pattern, wherein the second fluid droplet pattern is a non-integer multiple of the preset minimum pitch; determining an adjusted speed of the substrate and the fluid dispense ports relative to each other to generate the second fluid droplet pattern; moving the substrate and the fluid dispense ports relative to each other at the adjusted speed; and dispensing the formable material through the fluid dispense ports at the preset frequency to form the second fluid droplet pattern on the substrate.Type: GrantFiled: December 12, 2016Date of Patent: November 5, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Edward Brian Fletcher, Zhengmao Ye
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Patent number: 10446507Abstract: A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.Type: GrantFiled: August 30, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Hongbin Zhu, Qinglin Zeng, Daniel Osterberg, Merri L. Carlson, Gordon A. Haller, Jeremy Adams
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Patent number: 10446580Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.Type: GrantFiled: March 11, 2019Date of Patent: October 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Gn Yun, Sun Young Kim, Hoo Sung Cho
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Patent number: 10394221Abstract: Systems, devices, and methods are described herein for transforming three dimensional (3D) video data into a 3D printable model. In one aspect, a method for transforming 3D video data may include receiving 3D video data indicated or selected for 3D printing. The selected portion or 3D video data, which may include a frame of the 3D video data, may be repaired or modified to generate a 3D model that define at least one enclosed volume. At least one of the enclosed volumes of the 3D video data may be re-oriented based on at least one capability of a target 3D printing device. In some aspects, the re-orienting may be performed to optimize at least one of a total print volume or print orientation of the at least one enclosed volume. In some aspects, the method may be performed in response to a single selection or action performed by a user.Type: GrantFiled: August 12, 2016Date of Patent: August 27, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Kristofer N. Iverson, Patrick John Sweeney, William Crow, Dennis Evseev, Steven Craig Sullivan, Alvaro Collet Romea, Ming Chuang, Zheng Wang, Emmett Lalish
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Patent number: 10391503Abstract: A system and method for predicting a future wind direction and speed and, based thereon, determining a future wind-driven drift and providing the information to an operator or automatically acting to adapt application parameters to better control the wind-driven drift of a fluid during application of the fluid to land or crops by an agricultural machine. A processor receives machine and meteorological data, uses a model to predict the future wind direction and speed, and accesses a drift distance database to determine and visually depict the future wind-driven drift of the fluid. A sensitive area database stores information about sensitive areas bordering the target area, which may also be displayed, to facilitate controlling the wind-driven drift with regard to the sensitive areas. The mathematical model may be a kernel filter, an autoregressive model, an autoregressive integrated moving average model, or a hybrid model which incorporates features of different models.Type: GrantFiled: August 25, 2016Date of Patent: August 27, 2019Assignees: Iowa State University Research Foundation, Inc., AGCO CorporationInventors: H. Mark Hanna, Matthew Schramm, John Peterson, Jeffrey Michael Zimmerman
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Patent number: 10396021Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.Type: GrantFiled: April 11, 2018Date of Patent: August 27, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
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Patent number: 10396234Abstract: A package structure of a long-distance sensor includes a substrate, a light-emitting chip, a sensing chip, two packaging gel bodies, and a cap. The substrate has a bearing surface. The light-emitting chip and the sensing chip are disposed on the bearing surface and separated from each other. The two packaging gel bodies cover the light-emitting chip and the sensing chip respectively and are separated from each other. The cap is disposed on the bearing surface and the packaging gel bodies, fastened to the bearing surface and the packaging gel bodies by adhesive, and provided with a light-emitting hole located above the light-emitting chip and a light-receiving hole located above the sensing chip.Type: GrantFiled: December 4, 2017Date of Patent: August 27, 2019Assignee: Lingsen Precision Industries, Ltd.Inventors: Ching-I Lin, Ming-Te Tu
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Patent number: 10388829Abstract: The invention describes a radiation-emitting semiconductor component (100) having a first semiconductor layer sequence (10) which is designed to generate radiation of a first wavelength, a second semiconductor layer sequence (20), a first electrode area (1) and a second electrode area (2). It is provided that the second semiconductor layer sequence (20) has a quantum pot structure (21) with a quantum layer structure (22) and a barrier layer structure (23) and is designed to generate incoherent radiation of a second wavelength by means of absorption of the radiation of the first wavelength, and an electric field can be generated in the second semiconductor layer sequence (20) by the first electrode area (1) and the second electrode area (2).Type: GrantFiled: April 13, 2016Date of Patent: August 20, 2019Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Adam Bauer, Andreas Loeffler
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Patent number: 10388742Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).Type: GrantFiled: March 1, 2017Date of Patent: August 20, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Tatsuo Shimizu
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Patent number: 10381425Abstract: Provided is an organic light emitting display device having a protective substrate configured to minimize permeation of moisture or static electricity into the device. The protective substrate is disposed on the bottom surface of a substrate so as to support and protect a substrate having an organic light emitting diode from moisture.Type: GrantFiled: May 10, 2017Date of Patent: August 13, 2019Assignee: LG Display Co., Ltd.Inventors: Ji Yeon Kang, Il Chan Jung
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Patent number: 10373994Abstract: There is provided an image sensor having a plurality of pixels, each pixel including a light receiving portion configured to receive incident light, a waveguide configured to guide the incident light from a light incident surface to the light receiving portion, and a light shielding portion disposed between the light incident surface and the light receiving portion, for blocking the incident light. The light shielding portion has an opening formed near a light emitting surface of the waveguide. The light receiving portion receives the incident light passing through the waveguide and the opening. A width of a core of the waveguide and a width of the opening are set so that the widths increase as a wavelength of the light incident on a pixel becomes longer.Type: GrantFiled: August 21, 2013Date of Patent: August 6, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Takeshi Matsunuma
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Patent number: 10352913Abstract: In a GC×GC data processor (23), a modulation time estimation unit (24) creates a one-dimensional chromatogram from chromatogram data items collected by a comprehensive two-dimensional GC, and retrieves a shift time on which a peak position after an entire curve of the chromatogram being shifted in a temporal axis direction coincides with a peak position of the peak on the original chromatogram. Since the resolution of a primary column (12) is low, the same compound is introduced into a secondary column (14) in consecutive modulation times. Accordingly, on the one-dimensional chromatogram, peaks originating from the same compound appear in the respective consecutive modulation times. The interval between the peaks substantially coincides with the modulation time. Therefore, the shift time retrieved as described above is regarded as the modulation time.Type: GrantFiled: October 25, 2012Date of Patent: July 16, 2019Assignee: SHIMADZU CORPORATIONInventor: Megumi Hirooka
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Patent number: 10347680Abstract: A charge storage cell includes a semiconductor region having charge carriers of a first conductivity type, a first deep trench isolation structure, and a charge storage region located adjacent to the first deep trench isolation structure. The charge storage region has charge carriers of a second conductivity type different to the first conductivity type and extends along substantially all of the first deep trench isolation structure. A second deep trench isolation structure is located adjacent to the charge storage region and opposite the first deep trench isolation structure.Type: GrantFiled: October 3, 2018Date of Patent: July 9, 2019Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventor: Laurence Stark
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Patent number: 10347751Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.Type: GrantFiled: August 30, 2017Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 10332797Abstract: A method for fabricating a semiconductor device includes forming first gate stacks on a first region of a substrate to be spaced apart by a first distance, forming second gate stacks on a second region of the substrate to be spaced apart by a second distance greater than the first distance, forming a first blocking film along the first gate stacks and the substrate, a thickness of the first blocking film between the first gate stacks being a first thickness, forming a second blocking film along the second gate stacks and the substrate, a thickness of the second blocking film between the second gate stacks being a second thickness different from the first thickness, and removing the first blocking film, the second blocking film, and the substrate to form a first recess between the first gate stacks and a second recess between the second gate stacks.Type: GrantFiled: April 6, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yongkuk Jeong, Gi Gwan Park