Abstract: The present disclosure provides an organic light-emitting display panel and an organic light-emitting display device. The display panel includes gate lines; data lines intersecting with and insulated from the gate lines; light-emitting control lines; pixel units; gate drive units electrically connected to the gate lines, and light-emitting control units electrically connected to the light-emitting control lines. The gate drive units and the light-emitting control units are arranged along an arc, which has a curvature radius of R, where R>0. Each of the light-emitting control units corresponds to n gate drive units of the gate drive units, where n is an integer larger than 1. Each of the light-emitting control units includes m straight portions, where m is an integer and 1<m?n. An included angle between two adjacent straight portions of the m straight portions is smaller than 180°.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: Predicting maintenance needs and analyzing preventative maintenance requirements in electrically powered turbomachinery with multi-parameter sensors and power quality sensors, both of the Fog-type, providing time domain output data and transforming data samples into the frequency domain to detect a root cause of failure of the machinery.

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Abstract: The disclosure discloses a display panel, a display device, and a method for manufacturing the display panel, where a chip on film is adhered on a frame edge of a side of a display substrate away from a display face of the display substrate through an insulation adhesive, and then signal lines on a frame edge of the display face of the display substrate are connected with connection terminals arranged on a side of the chip on film away from the display substrate through an electrically conductive material in a plurality of connection holes running through the display substrate, the insulation adhesive and the chip on film, so a pad bending process can be dispensed with, and there will be no pad bending area on the frame edge of the display panel, thus further narrowing a bezel of the display panel.

Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.

Abstract: An array substrate (200), a fabrication method of the array substrate (200), and a display panel and an electronic device having the array substrate (200) are provided. The array substrate (200) includes a base substrate (201), and a gate line (202), an insulating layer (204), a data line (208), and a first active pad layer (216) provided on the base substrate (201); wherein, the insulating layer (204) is provided on the gate line (202), the data line (208) is arranged on the gate line (202) through the insulating layer (204) and is arranged intersecting with the gate line (202), the first active pad layer (216) is arranged on the gate line (202) through the insulating layer (204) and is arranged overlapping with the gate line (202), and the first active pad layer (216) is arranged outside a region where the gate line (202) and the data line (208) overlap with each other.

Abstract: A magnetic field effect transconductor device (M-FET) capable of carrying a modulated current when receiving an external magnetic field includes at least a ferromagnetic layer and a non-ferromagnetic layer disposed on the ferromagnetic layer; the non-ferromagnetic layer has a first skin depth of the current and a first thickness smaller than the first skin depth; and the ferromagnetic layer has a second skin depth of the current and a second thickness smaller than the second skin depth. Applying an external DC magnetic field along the longitudinal axis of the device and an AC EM wave propagating in the same direction as the DC field, the M-FET demonstrates frequency dependent current switching device. A method for making the transconductor includes depositing a photoresist over transconductors and patterning the photoresist, or depositing transconductors over a patterned photoresist and performing a lift off process.

Abstract: In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.

Abstract: A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.

Abstract: A method of manufacturing a light emitting device includes: providing a semiconductor stack including a first semiconductor layer and a second semiconductor layer; forming light emitting cells by forming grooves in column and row directions; exposing a portion of the first semiconductor layer from the second semiconductor layer in each light emitting cell; forming a first insulation layer having a first hole on the light emitting cells and the grooves; forming a wiring electrode to be in electrical connection with the first semiconductor layer at the first hole in each light emitting cell; forming a second hole in the first insulation layer; forming a second electrode to be in electrical connection with the second semiconductor layer at the second hole; thinning the first semiconductor layer; and exposing the first insulation layer from the first semiconductor layer at the grooves while roughening the surface of the first semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, first and second electrodes, second and third insulating units, and gate electrodes provided in the first semiconductor region and the second semiconductor region via a first insulating unit and extending in a first direction. The first electrode is provided on and electrically connected to the third semiconductor region. The second insulating unit is spaced apart from the gate electrodes in the first semiconductor region and extends in a second direction. The third insulating unit includes an insulating portion extending in the first direction and positioned between the gate electrodes and the second insulating unit in the second direction. The second electrode is electrically connected to the gate electrodes and provided on the second and third insulating units.

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.

Abstract: An assembly includes a ported component that includes a bore, radial passages, and axial passages; and a shifting sleeve that comprises a bore, radial passages, seal bosses and associated seal elements that define at least one sealed region with respect to the radial passages of the ported component and that define an open region with respect to the radial passages of the ported component.

Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.

Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.