Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: A manufacturing method of the light-emitting diode package structure is provided. A carrier is formed. The carrier comprises a first build-up circuit. At least one self-assembled material layer is formed on the first build-up circuit. A first solder mask layer is formed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the at least one self-assembled material layer. At least one light-emitting diode is disposed on the first build-up circuit. The at least one light-emitting diode has a self-assembled pattern, and the at least one light-emitting diode is self-assembled into the at least one opening of the first solder mask layer through a force between the self-assembled pattern and the at least one self-assembled material layer.

Abstract: A display device includes: a substrate including a display area at which an image is displayed; and on the substrate in the display area thereof: a data line and a gate line on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a storage line which overlaps the pixel electrode. The storage line has a first hole at a position overlapping the data line.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.

Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

Abstract: Provided is a small-sized power semiconductor device in which interference between power modules adjacently disposed is prevented and the areas of the gaps occurring between the power modules are reduced. In a power semiconductor device formed by adjacently disposing power modules in an arc shape on a heat sink, each of which power modules is obtained by sealing, with a mold resin, a switchable power semiconductor chip, a lead frame in which potential leads and signal terminals connected to the power semiconductor chip are formed, and a metallic inner lead electrically connecting an upper surface electrode of the power semiconductor chip and the lead frame, any one of the adjacent power modules is formed in a pentagonal shape having, at a portion adjacent to the other power module, an oblique side 10a obtained by cutting out one corner of a quadrangle.

Abstract: A wiring substrate includes: a first insulating layer; a plurality of wiring patterns formed on one surface of the first insulating layer; a dummy pattern formed, on the one surface of the first insulating layer, between the nearby wiring patterns; and a second insulating layer made of resin and formed on the one surface of the first insulating layer so as to cover the nearby wiring patterns and the dummy pattern, wherein the dummy pattern is a dot pattern arranged at a center portion between the nearby wiring patterns, and wherein a height of at least one dot constituting the dummy pattern is lower than heights of the nearby wiring patterns.

Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Abstract: A display substrate comprises a base board and a first bonding pad. The base board comprises a first surface having a first bonding district. The first bonding pad is disposed on the first surface. The first bonding pad is configured to electrically connect to a first electrode of a light emitting component in the first bonding district. The first bonding pad comprises a main bonding portion and an auxiliary bonding portion, wherein at least a part of an orthogonal projection of the main bonding portion on the base board is in the first bonding district. The auxiliary bonding portion electrically connects to the main bonding portion, wherein at least a part of an orthogonal projection of the auxiliary bonding portion on the base board is outside the first bonding district. There is a gap between the main bonding portion and the auxiliary bonding portion.

Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.

Abstract: The present invention generally describes one ore more methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted damage created from prior processing steps (e.g., crystal damage from implant processes), more evenly distribute dopants in various regions of the substrate, and/or activate various regions of the substrate. The preferential melting processes will allow more uniform distribution of the dopants in the melted region, due to the increased diffusion rate and solubility of the dopant atoms in the molten region of the substrate. The creation of a melted region thus allows: 1) the dopant atoms to redistribute more uniformly, 2) defects created in prior processing steps to be removed, and 3) regions that have hyper-abrupt dopant concentrations to be formed.

Abstract: A display device including: a first substrate; a first conductive line disposed on the first substrate; an insulating layer disposed on the first conductive line; a second conductive line disposed on the first conductive line and the insulating layer; a protective layer disposed on the second conductive line; a plurality of first contact holes defined by the insulating layer and the protective layer; a plurality of second contact holes defined by the protective layer; and a conductive layer disposed over the plurality of first contact holes and the plurality of second contact holes, and connecting the first conductive line and the second conductive line. The plurality of first contact holes and the plurality of second contact holes are arranged alternately along a first direction and along a second direction which intersects the first direction.

Abstract: A light source includes a light emitting element configured to emit a light; a mounting substrate; and a ceramic substrate having a light emitting element mounted thereon and being bonded to the mounting substrate via a plurality of metal bumps made of gold, copper, a gold alloy, or a copper alloy. A method of manufacturing a light source includes forming a plurality of metal bumps on a mounting substrate; providing a ceramic substrate having at least one light emitting element mounted thereon; and bonding the mounting substrate and a ceramic substrate to each other via the metal bumps.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including at least a hardmask having a first layer and a second layer, the second layer being a ruthenium layer, and removing the first layer of dual layer hardmask during a via opening such that the ruthenium layer remains intact to protect the RRAM stack during a damascene process.

Abstract: A method of manufacturing a light-emitting device includes applying a light-guiding member to a light-emitting element. A light-transmissive member is mounted on the light-guiding member, and the light-guiding member is cured. A width of the light-transmissive member is narrowed. Lateral surfaces of the light-transmissive member and lateral surfaces of the light-guiding member are covered.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Abstract: The present application provides a method for fabricating a back channel etching oxide semiconductor TFT substrate, by depositing the first passivation layer on the source, the drain and the active layer, and treating the oxygen element containing plasma to a surface of the first passivation layer, infiltrating traces of oxygen element into the superficial layer of the channel region of the active layer through the first passivation layer, then using an oxygen element containing plasma to treat the surface of the first passivation layer, so that the traces of oxygen element infiltrates into the superficial layer of the channel region of the active layer via the first passivation layer, to supply the oxygen element to the superficial layer of the channel region, and ensure the oxygen element balance in the superficial layer, the first passivation layer acts as a barrier layer to ensure the stability of the TFT.

Abstract: A package includes a first lead electrode, a second lead electrode, and a resin molded body. The first lead electrode has a first upper surface and a first lower surface defining a depression and opposite to the first upper surface. The second lead electrode has a second upper surface and a second lower surface opposite to the second upper surface. The resin molded body defining a recess with a bottom surface including the first upper surface and the second upper surface, the resin molded body also covering the first lower surface and the second lower surface. The first electrode having a first region closer to the second lead electrode and a second region farther to the second lead electrode than the first region, and having a thickness smaller than a thickness of the first region due to the depression defined in the first lower surface.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.