Patents Examined by Amir Zarabian
  • Patent number: 10803919
    Abstract: A memory system includes a memory module comprising a plurality of memory devices, and a memory controller suitable for controlling the plurality of memory devices to perform a refresh operation or performing an error correction code (ECC) operation on the plurality of memory devices, according to a refresh operation request.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventors: Joon-Woo Kim, Hyun-Seok Kim, Young-Jae Jin
  • Patent number: 10706912
    Abstract: Memory might include control logic configured to apply an erase pulse to a data line and to a common source concurrently with applying a higher second voltage level to a control gate of a transistor connected between the data line and the common source, concurrently discharge the voltage level of the data line and the voltage level of the common source, monitor a representation of a voltage difference between the voltage level of the data line and the voltage level of the control gate of the transistor, activate a current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be greater than a first value, and deactivate the current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be less than a second value.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10672471
    Abstract: A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with a set of row lines and a set of column lines.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Masatoshi Ishii, Kohji Hosokawa, Atsuya Okazaki, Akiyo Iwashina
  • Patent number: 10672445
    Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Il O, Jun Hyung Kim, Kyo Min Sohn
  • Patent number: 10586589
    Abstract: There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: March 10, 2020
    Assignee: SURECORE LIMITED
    Inventor: Andrew Pickering
  • Patent number: 10586587
    Abstract: According to one embodiment, semiconductor memory device includes a first circuit that determines data stored in a memory cell; and a second circuit that controls the first circuit, wherein in a sequence in which the second circuit writes first data in the memory cell, the first circuit generates a first current of a first current value, and determines data stored in the memory cell based on the first current and a second current flowing in the memory cell, and in a sequence in which the second circuit writes second data different from the first data in the memory cell, the first circuit generates a third current of a second current value different from the first current value, and determines data stored in the memory cell based on the third current and the second current.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 10, 2020
    Assignees: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiaki Dozaka
  • Patent number: 10573378
    Abstract: Methods of operating non-volatile memory devices are provided including receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Seop Shim, Jae-Hong Kim, Jin-Man Han
  • Patent number: 10572381
    Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
  • Patent number: 10552313
    Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
  • Patent number: 10515675
    Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Sung-Eun Lee, Jung-Hyun Kwon
  • Patent number: 10497416
    Abstract: A spintronic memory device having a spin momentum-locking (SML) channel, a nanomagnet structure (NMS) disposed on the SML, and a plurality of normal metal electrodes disposed on the SML. The magnetization orientation of the NMS is controlled by current injection into the SML through normal metal electrode. The magnetization orientation of the NMS is determined by measuring voltages across the NMS and the SML while flowing charge current through the SML via the normal metal electrodes.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 3, 2019
    Assignee: Purdue Research Foundation
    Inventors: Shehrin Sayed, Supriyo Datta, Esteban E. Marinero-Caceres
  • Patent number: 10490246
    Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 26, 2019
    Assignee: SK HYNIX INC.
    Inventors: Sang Hyun Ku, HongJung Kim
  • Patent number: 10453529
    Abstract: This invention introduces a resistive random access memory (RRAM) device, a write verify method and a reverse write verify thereof which are capable of improving the performance of RRAM operations and improving the uniform performance for each RRAM cell. A first resistance value sensed from a RRAM cell is compared with a plurality of reference resistance values to obtain a comparison value. A set or a reset operation is performed on the RRAM cell by applying a first set or reset pulse to change the first resistance value to a second resistance value. Next, the second resistance value is compared with the comparison value to determine whether to continue the set or reset operation on the RRAM cell.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 22, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Koying Huang
  • Patent number: 10424348
    Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryota Suzuki, Tatsuo Izumi
  • Patent number: 10395699
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 27, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 10388364
    Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka
  • Patent number: 10340002
    Abstract: A resistive processing unit (RPU) device includes a weight storage device to store a weight voltage which corresponds to a weight value of the RPU device, and a read transistor having a gate connected to the weight storage device, and first and second source/drain terminals connected to first and second control ports, respectively. A current source connected to the second source/drain terminal generates a fixed reference current. The read transistor generates a weight current in response to the weight voltage. A read current output from the second control port represents a signed weight value of the RPU device. A magnitude of the read current is equal to a difference between the weight current and the fixed reference current. The sign of the read current is positive when the weight current is greater than the fixed reference current, and negative when the weight current is less than the fixed reference current.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Hyung-Min Lee, Tayfun Gokmen, Shu-Jen Han
  • Patent number: 10332573
    Abstract: A semiconductor device includes a comparison circuit suitable for comparing a reference voltage and a strobe signal, and generating a first comparison strobe signal. The semiconductor device also includes a reference voltage training circuit suitable for sequentially changing a voltage level of the reference voltage if a training mode is entered, and setting the voltage level of the reference voltage by sensing a duty ratio of the first comparison strobe signal.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventor: Yun Gi Hong
  • Patent number: 10297330
    Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 21, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Henry Chin, Yingda Dong
  • Patent number: 10079062
    Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: September 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoji Kashihara