Abstract: Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.

Abstract: A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract: A memory device includes: a memory element which includes three or more resistance states by using plural magneto-resistive elements each having a first resistance state or a second resistance state; and a comparison and determination circuit which compares the resistance states of the memory element before and after one first magneto-resistive element from among the plural magneto-resistive elements in the memory element is rewritten into the first resistance state, and determines the resistance state of the memory element in accordance with the comparison result.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Abstract: A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl.

Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract: A latch circuit that latches stored data of a nonvolatile storage device used for setting the function of a semiconductor device and adjusting the characteristics of the semiconductor device required a dedicated input-output circuit for a test of the semiconductor device. By providing a dummy storage device, it becomes possible to perform a test of the semiconductor device without providing a dedicated input-output circuit.

Abstract: A programming method of a semiconductor memory device includes, in an n-th program loop, applying a first program pulse to a first memory cell group, applying a second program pulse to a second memory cell group, and determining first fast cells and first slow cells in the first memory cell group, and in an n+1-th program loop, applying a third program pulse, which is increased by a step voltage from the first program pulse, to the first fast cells in the first memory cell group, and applying a fourth program pulse, which is increased by the step voltage from the second program pulse, to the first slow cells in the first memory cell group and the second memory cell group.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract: A data transmission circuit includes an input line selection unit configured to transfer data of a selected input line among a plurality of input lines to an output line, a data sensing unit connected to the plurality of input lines and configured to sense the data of the selected input line, and a data amplification unit configured to amplify data of the output line in response to a data sensing result of the data sensing unit.

Abstract: A magnetic random access memory includes multiple gate lines that are divided into a first gate line group and a second gate line group and arranged to be parallel to one another; multiple magnetic random access memory cells that are bonded to the gate lines in a direction intersected with the gate lines, respectively; multiple source lines that are bonded to one ends of switching devices included in the magnetic random access memory cells and arranged to be parallel to one another; and multiple bit lines that are bonded to one ends of magnetic tunnel junction devices included in the magnetic random access memory cells and arranged to be parallel to one another.

Abstract: The semiconductor device includes a control signal driver, a control signal latch unit, an internal driver and a buffer. The control signal driver drives a control signal in response to a fuse reset signal, a fuse set signal and a fuse data. The control signal latch unit is suitable for latching the control signal. The internal driver drives an internal node in response to the control signal, an address signal and a write strobe signal. The buffer buffers a signal of the internal node to generate the redundancy signal.

Abstract: A memory apparatus includes a plurality of gated phase-change memory cells having s?2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only.

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

Abstract: A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ.