Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

Abstract: A resistive processing unit (RPU) device includes a weight storage device to store a weight voltage which corresponds to a weight value of the RPU device, and a read transistor having a gate connected to the weight storage device, and first and second source/drain terminals connected to first and second control ports, respectively. A current source connected to the second source/drain terminal generates a fixed reference current. The read transistor generates a weight current in response to the weight voltage. A read current output from the second control port represents a signed weight value of the RPU device. A magnitude of the read current is equal to a difference between the weight current and the fixed reference current. The sign of the read current is positive when the weight current is greater than the fixed reference current, and negative when the weight current is less than the fixed reference current.

Abstract: A semiconductor device includes a comparison circuit suitable for comparing a reference voltage and a strobe signal, and generating a first comparison strobe signal. The semiconductor device also includes a reference voltage training circuit suitable for sequentially changing a voltage level of the reference voltage if a training mode is entered, and setting the voltage level of the reference voltage by sensing a duty ratio of the first comparison strobe signal.

Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.

Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).

Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material having a fixed magnetization direction, along with a free layer formed from a free layer material having a switchable magnetization direction. The MTJ is configured to receive a write pulse having a write-pulse and spin-transfer-torque (WP-STT) start time, a WP-STT start segment duration and a write pulse duration. The WP-STT start segment duration is less than the write pulse duration. The fixed magnetization direction is configured to form an angle between the fixed magnetization direction and the switchable magnetization direction. The angle is sufficient to generate spin torque electrons in the reference layer material at the WP-STT start time. The spin torque electrons generated in the reference layer material is sufficient to initiate switching of the switchable magnetization direction at the WP-STT start time.

Abstract: Systems, methods and/or devices that enhance the reliability with which data can be stored in and read from a memory utilize an error indicator, obtained from using one reading threshold voltage for decoding, to adaptively determine the reading threshold voltage(s) used for subsequent decoding attempts. For example, in some implementations, the method includes initiating performance of a first read operation, using a first reading threshold voltage, to obtain a first error indicator, and further includes initiating performance of a second set of additional read operations using two or more second reading threshold voltages, the second reading threshold voltages determined in accordance with the first error indicator, to obtain a second error indicator. In some embodiments, when the first error indicator is greater than a first threshold, a difference between two of the second reading threshold voltages is greater than when the first error indicator is less than a first threshold.

Abstract: A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.

Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

Abstract: A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. The second and third pads may receive a second external voltage. The second pad may provide the second voltage, and the third pad may provide the third voltage.

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: A semiconductor memory includes: a plurality of input/output terminals that can be switched between being a plurality of common input/output terminals capable of bidirectionally transmitting data and a plurality of separate input/output terminals including a plurality of dedicated input terminals that receives data and a plurality of dedicated output terminals that outputs data; and a control circuit that switches the common input/output terminals and the separate input/output terminals based on input/output terminal setting information issued with each access command that controls reading from a memory cell or writing to the memory cell, the switched terminals being used to transmit data read out from the memory cell or data written to the memory cell according to the access command.

Abstract: A memory system has a first plurality of non-volatile random access memory (NVRAM) cells. Each NVRAM cell has a volatile portion coupled to a corresponding non-volatile portion. A non-volatile indicator circuit provides information as to whether the first plurality of NVRAM cells has the most recent data written into NVRAM cells in the non-volatile portions.

Abstract: Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is described herein. In some embodiments, one time programmable, multi-level cell two-terminal memory cell can exhibit diode-like characteristics. In other embodiments, the memory cell can comprise a first electrode layer configured to generate ions in response to an electric field applied to the memory cell; a resistive ion migration layer at least in part permeable to migration of the ions within the resistive ion migration layer; a second electrode layer; and a substrate layer comprising a silicon wafer.

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract: A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell (1) array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WL1 to WLn), the memory cells in a column are connected at the other end to common bit lines (BL1 to BLm), and a common unselected voltage VWE/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.