Abstract: A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plurality of word lines. A driver region separates the first and second regions and includes word line driver circuits coupled to the word lines of the first and second memory sub-arrays. A row decoder region adjacent the first region and separate from the driver region includes at least some sub-circuits of row decoder circuits located therein. The row decoder circuits are coupled to the word line driver circuits located in the driver region and are configured to activate driver circuits to drive word lines of the first and second memory sub-arrays in response to decoding address signals selecting the particular row decoder circuit.

Abstract: A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

Abstract: A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first and second data are respectively read out, in the column direction. When one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after data read out, the potential of the other bit line is changed from the second to the first potential, and if the electric potential of the selected bit line changes from the first to the second potential when data is read out, the other bit line is selected when the data is next read out, and, if the electric potential of the selected bit line maintains the first potential, the selected bit line is maintained selected even when the data is to be read out next.

Abstract: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.

Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

Abstract: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.

Abstract: A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.

Abstract: The present invention provides a high-capacity and reliable semiconductor device which does not require additional circuits for use at power ON/OFF, additional steps nor high manufacturing cost, and which has a rectifier means for rectifying a defect easily. A semiconductor device comprises a first memory means including a memory cell and a redundant memory cell each including a memory element in the region where a bit line and a word line cross each other with an insulator interposed therebetween, a second memory means for storing an address of a defective memory in the first memory means, a rectifier means including a holding means and a replacement means, and an inspection means for writing data of the second memory means to the holding means. The replacement means replaces the defective memory cell with the redundant memory cell. In addition to the aforementioned four means, a display means for displaying images is provided as well.

Abstract: A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.

Abstract: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.

Abstract: Disclosed herein are a magnetic memory device and method for storing and retrieving data. The magnetic memory device includes a read disk and a storage disk. The read disk comprises of an array of read heads wherein the individual read head corresponds to a storage element on the storage disk.

Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

Abstract: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.

Abstract: An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a read operation is performed and column current is detected, a high-efficiency recovery operation is performed. If the read operation is performed and column current is not detected, the erase operation has been successfully completed.

Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.

Abstract: We describe a semiconductor memory device including a memory cell array and a storage device to store access data. The memory cell array is accessed responsive to the access data. The memory cell array access is determined by the access data stored in the storage device. The memory cell array is accessed according to access data only if necessary, drastically reducing power dissipation.

Abstract: A nonvolatile semiconductor memory device is provided comprising a plurality of memory cell arrays, each of which consists mainly of sidewall type memory cells arranged in a matrix, the memory cell having a MOSFET structure where memory functional element for holding charges are provided on both sides of a gate electrode. The memory cell array is divided into sectors. The memory device further comprises a sector selecting circuit for, when one of the memory cell arrays is to be erased collectively, sequentially selecting at most a predetermined number of the sectors at a time from the memory cell array to be erased, and an erase voltage applying circuit for, when the collective erasing action is carried out, applying a predetermined level of erasing voltage to the sectors selected at once by the sector selecting circuit.