Abstract: A semiconductor integrated circuit device includes a memory cell array, an address transition detecting circuit which detects transition of a column address signal, the column address signal being used to specify a column address of the memory cell array, a control circuit having a timeout circuit, the control circuit which generates an internal circuit control signal of desired length used to control column access to the memory cell array based on a result of detection by the address transition detecting circuit, and a column selection line whose selection time is controlled by the control circuit, wherein the column address signal used for selection of the column selection line is latched in a period of time in which the column selection line is selected at a write operation time.

Abstract: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.

Abstract: First and second internal power source lines supply first and second voltages to an internal circuit, respectively. A first line 31 and a second line 32 are arranged parallel to the first and the second internal power source lines in a layer above the layer in which the first and the second internal power source lines are arranged. Third lines 33 extend in a direction perpendicular to the first line in a layer above the layer in which the first and the second internal power source lines are present. Fourth lines 34 extend in a direction perpendicular to the second line in a layer above the layer in which the first and the second internal power source lines are present. The first, and the third and the first internal power source lines are connected, and the second, and the fourth and the second internal power source lines are connected.

Abstract: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

Abstract: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.

Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Abstract: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

Abstract: Disclosed herein is a NAND flash memory device capable of changing a block size. In NAND flash memory devices capable of changing a block size, each memory block is divided into two page groups. Each memory block includes two block switches to select each page group in response to an external address signal. During an erasing operation, the block size is easily variable by applying an erasure voltage to one or two page groups.

Abstract: When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corresponding to the command.

Abstract: A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for logically combining a word line signal with a column address signal and providing the resulting output signal to the gates of the access transistors. In one embodiment, the logic gate is a NOR logic gate and in another embodiment, the logic gate is a transmission gate. This prevents a potential read disturb problem with unselected memory cells of a row. This also reduces power consumption in the memory.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells, providing a bit line, providing a plurality of word lines, providing bit line read/write logic, and providing a plurality of switches for the bit line. Each of the magnetic storage cells includes a magnetic storage element capable of being programmed by a write current driven through the magnetic storage element. The bit line corresponds to the magnetic storage cells. Each of the word lines corresponds to a magnetic storage cell of the magnetic storage cells and allows current to flow through the magnetic storage cell. The bit line read/write logic corresponds to the bit line. The switches are for the bit line and controlled by the bit line read/write logic to selectively provide a read current or the write current to the magnetic storage elements.

Abstract: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.

Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

Abstract: A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less “0” values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.

Abstract: A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.

Abstract: A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The first memory cell array includes lower electrodes formed in stripes, upper electrodes formed in stripes in a direction that crosses the lower electrodes, ferroelectric capacitors that are disposed at least at intersecting parts of the lower electrodes and the upper electrodes, and an embedded insulating layer formed between the ferroelectric capacitors. The interlayer insulating layer includes a conductive layer between a first insulating layer and a second insulating layer.