Patents Examined by An T. Luu
  • Patent number: 10411680
    Abstract: A circuit includes a first TSCP (tri-state charge pump) configured to receive a first phase and a third phase of a six-phase signal; a second TSCP configured to receive a second phase and a fourth phase of the six-phase signal; a third TSCP configured to receive a third phase and a fifth phase of the six-phase signal; a fourth TSCP configured to receive a fourth phase and a sixth phase, a fifth TSCP configured to receive the fifth phase and the first phase, and a sixth TSCP configured to receive the sixth phase and the second phase of the six-phase signal. The first, third, and fifth TSCPs output currents to a first output node and the second, fourth, and sixth TSCPs output currents to a second output node. A load is placed across the first output node and the second output node.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 10, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10411720
    Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: MAX-PLANCK-GESELLSCHAFT ZUR FÖRDERUNG DER WISSENSCHAFTEN E.V.
    Inventors: Christoph Lenzen, Matthias Függer, Attila Kinali, Stephan Friedrichs, Moti Medina
  • Patent number: 10404235
    Abstract: Power transfer systems including a direct current source and a plurality of outputs operable in several modes. A ground mode may couple an output to circuit ground and a current mode may couple the output to the direct current source. The power transfer system may also include a controller configured to iteratively select a pair of outputs from the plurality of outputs. Once a pair is selected, the controller may set a first output of the pair of outputs to the current mode and the second to ground mode for a determined duration. After the duration has passed, the controller may set the first output to the ground mode and the second output to the current mode for the same duration. Thereafter the controller may select another pair of outputs.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 3, 2019
    Assignee: APPLE INC.
    Inventors: Brian C. Menzel, Jeffrey M. Alves, Kevin M. Keeler, Zachary C. Rich
  • Patent number: 10404164
    Abstract: A system may include first and second node, switch, driver, capacitor, and second driver. The first node may be at first voltage. The second node may be at second voltage. The switch may be coupled to the second node and output of the second driver and configured to receive input at third voltage and voltage at fourth voltage and to provide the input to the second node when the fourth voltage is greater than the third voltage. The driver may be coupled to the first and second nodes and configured to receive driver input and to generate intermediate voltage based on the driver input. The capacitor may be coupled to the driver to shift the intermediate voltage. The second driver may be coupled to the second node and the driver and configured to receive second driver input and the shifted intermediate voltage to generate the voltage at the fourth voltage.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Smart Prong Technologies, Inc.
    Inventor: Brian Stevenson
  • Patent number: 10396776
    Abstract: This disclosure describes a gate driver with voltage boosting capabilities. In some embodiments, the gate driver may comprise a charge pump that includes capacitor(s) and switch(es). Responsive a logic low input signal, the gate driver may bypass the capacitor(s) to allow the input digital signal to drive the gating signal directly. Conversely, responsive to a logic high input signal, the gate driver may couple the capacitor(s) in series with the input digital signal to generate a boosted gating signal. In some embodiments, the gate driver may comprise an inductor-capacitor resonant circuit to create a doubled output gating signal with respect to the input digital signal. In some embodiments, the resonant gate driver may include an additional voltage boosting capability that can be selectively enabled to compensate for a voltage drop during the signal transfer from the input to the output.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 27, 2019
    Assignee: Apple Inc.
    Inventors: Marco A. Davila, Bogdan T. Bucheru
  • Patent number: 10396782
    Abstract: A technique relates to a microwave switch. A first nondegenerate device includes a first port and a second port. A second nondegenerate device includes another first port and another second port, the second port being coupled to the another second port, where the first nondegenerate device and the second nondegenerate device are configured to receive a phase difference in microwave drives. A first input/output port is coupled to the first port and the another first port. A second input/output port is coupled to the first port and the another first port, where communication between the first input/output port and the second input/output port is based on the phase difference.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10389351
    Abstract: Reverse recovery current flowing through a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having been turned off can become reverse recovery loss. Reverse recovery loss of the MOSFET is desirably reduced. A semiconductor apparatus including: a MOSFET portion; and a diode portion connected in anti-parallel with the MOSFET portion, wherein reverse recovery current flows through the diode portion after reverse recovery current of the MOSFET portion becomes zero is provided.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuaki Sakai
  • Patent number: 10389369
    Abstract: An apparatus is comprised of a processor, a tuning voltage generator, a tuning circuit, an amplifier, and a voltage-controlled oscillator (VCO). The processor generates a tuning voltage command and a modulation command signal. The tuning voltage generator, coupled to the processor, receives the tuning voltage command and generates a baseline analog tuning signal based on the received tuning voltage command. The amplifier, coupled to the tuning voltage generator, receives the baseline analog tuning signal and the modulation signal, and generates a tuning signal based on the received baseline analog tuning signal and the received modulation command signal. The VCO, coupled to the amplifier, receives the tuning signal, generates a modulated radio frequency output signal based on the received tuning signal, and outputs the modulated radio frequency output signal, the modulated radio frequency output signal emulating a communication waveform.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 20, 2019
    Assignee: IXI TECHNOLOGY HOLDINGS, INC.
    Inventors: Daniel Hyman, Jeffrey Norris, Joe Truong, Michael Dekoker, Anthony Aquino
  • Patent number: 10389359
    Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Hosaka, Satoru Sugimoto, Hayato Oishi
  • Patent number: 10382042
    Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 13, 2019
    Assignee: IMEC vzw
    Inventors: Roeland Vandebriel, Geert Van der Plas, Vladimir Cherman
  • Patent number: 10374651
    Abstract: An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: August 6, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shyam Sundar Sivakumar, Kevin Jia-Nong Wang
  • Patent number: 10374512
    Abstract: In a power converter, each gate-driving circuit uses charge from a selected pump capacitor operate a corresponding switch. The switches transitions between different states, each of which corresponds to a particular interconnection of pump capacitors. During clocked operations, the first switch closes, thereby establishing a connection with the first pump capacitor. Prior to the first switch closing, the second switch closes.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 6, 2019
    Assignee: pSemi Corporation
    Inventors: Gregory Szczeszynski, David M. Giuliano, Raymond Barrett, Jr.
  • Patent number: 10367516
    Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 30, 2019
    Assignee: Analog Devices Global
    Inventors: Frederick Carnegie Thompson, Varun Agrawal, Jose Barreiro Silva, Declan M. Dalton
  • Patent number: 10367494
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 30, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 10367499
    Abstract: A power supply ready indicator circuit is described. The power supply ready indicator circuit includes a first power-supply-ready-input interfacing with a first power supply rail; a second power-supply-ready-input interfacing with a second power supply rail; and a power ready indicator output. The power supply ready indicator circuit is configured to divide the voltage on the first power supply rail, and to compare the divided voltage with the second power supply rail voltage. The power supply ready indicator circuit generates a power ready signal on the power ready indicator output in response to the divided voltage value being greater than the second power supply rail voltage value. The final value of the first power supply rail voltage is greater than the final value of the second power supply rail voltage.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 30, 2019
    Assignee: NXP B.V.
    Inventors: Gian Hoogzaad, Amin Hamidian, Fanfan Meng
  • Patent number: 10361683
    Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Teruaki Kanzaki
  • Patent number: 10361473
    Abstract: A bidirectional coupler includes a first main line that transmits a first signal from a first input end thereof to a first output end thereof, a second main line that transmits a second signal from a second input end thereof to a second output end thereof, a first sub-line having a first end corresponding to the first input end and a second end corresponding to the first output end, a second sub-line having a first end corresponding to the second input end and a second end corresponding to the second output end, a detector port, a termination circuit, and a switch circuit. The first end of the first sub-line and the first end of the second sub-line are connected to each other.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroshi Okabe
  • Patent number: 10355661
    Abstract: A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form, an anti-resonance tuning circuit has a first node conductively coupled to one of the IC die's positive or negative power supply conductors, and a second node conductively coupled directly to a selected conductive structure on the carrier substrate. The anti-resonance tuning circuit includes a tuning capacitor, a tuning inductor, and optionally a dampening resistor coupled in series and having values sufficient to mitigate the die package resonance. In another form, impedance adjustment techniques are provided to connect and tune the anti-resonance tuning circuit to lower an impedance peak.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 16, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Fei Guo
  • Patent number: 10351080
    Abstract: An arrangement (1) is provided for electrically connecting a movable structural component of a motor vehicle mounted on a central unit with electrical elements in a body of a motor vehicle. The movable structural component is pivotally fastened about at least two points of rotation (12) to an axis of rotation (9?) on the vehicle body. A number of electrical elements are connected to the electrical lines fastened to a cable set (2) which is partially mounted in a free space between the vehicle body and the movable structural component. The cable set (2) is arranged and secured with a straight configuration between two points of rotation (12) surrounded by a protective element. The center axis (9?) of the cable set (2) corresponds at least partially to the axis of rotation of the movable component.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 16, 2019
    Assignee: NEXANS
    Inventors: Hermann Teicher, Gerhard Lindner, Helmut Steinberg
  • Patent number: 10348124
    Abstract: Automatic transfer switch and power supply units (ATSPSUs) and related methods condition switching to a second AC power source to allow a battery module to supply DC power to a load. An ATSPSU includes a power supply unit (PSU), an automatic transfer switch (ATS), and an ATSPSU controller configured to control the ATS to switch to the second AC power source in response to the voltage of the first AC power source having decreased in magnitude by a voltage drop value over a period of time greater than an allowable amount of time for the voltage drop value, and at least one of a voltage differential between DC power supply lines being less than a voltage threshold value, and a state of charge of a battery module operatively coupled with the DC power supply lines being less than a threshold state of charge.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 9, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mike MacGregor, Darin Lee Frink, Richard Arvel Stevens, William Mische