Abstract: A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

Abstract: Systems and methods for ensuring that resonant inductive power transfer goes only to authorized users using encryption. Resonant inductive power transfer requires near-identical resonant frequencies in the transmitter and the receiver. The frequency of the power transfer signal changes on a schedule known only to the transmitter and receiver so a “power eavesdropper” cannot track the frequency well enough to efficiently receive power. To make the frequency transitions energetically efficient, a capacitive or inductive element is switched in or out of each circuit at moments of zero-crossing: zero charge on a capacitor or zero current in an inductor. To maintain phase alignment, either switching an inductor on the transmit side is nearly simultaneous with switching a capacitor on the receive side, or switching a capacitor on the transmit side is nearly simultaneous with switching an inductor on the receive side.

Abstract: A switching module configured to apply power to a device is described. The switching module may comprise a first plurality of contact elements adapted to receive power and apply to power to the device in response to a control signal; a recess adapted to receive a control module; a second plurality of contact elements positioned within the recess and adapted to be coupled to corresponding contact elements of the control module; and a switching element that controls the application of the power to the device in response to a control signal; wherein the switching module is adapted to receive data from the control module to determine whether the control module is authorized to operate with the switching module.

Abstract: A noise suppressor includes a first differential-mode transmission module, a second differential-mode transmission module and a common-mode absorption module. The first and second differential-mode transmission modules are configured to receive a differential signal at one of the first and second differential-mode transmission modules, and output the differential signal at the other of the same. The common-mode absorption module is electrically connected to a reference node, and is configured to absorb common-mode noise of the differential signal from at least one of the first differential-mode transmission module or the second differential-mode transmission module.

Abstract: Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.

Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided.

Abstract: This disclosure describes a gate driver with voltage boosting capabilities. In some embodiments, the gate driver may comprise a charge pump that includes capacitor(s) and switch(es). Responsive a logic low input signal, the gate driver may bypass the capacitor(s) to allow the input digital signal to drive the gating signal directly. Conversely, responsive to a logic high input signal, the gate driver may couple the capacitor(s) in series with the input digital signal to generate a boosted gating signal. In some embodiments, the gate driver may comprise an inductor-capacitor resonant circuit to create a doubled output gating signal with respect to the input digital signal. In some embodiments, the resonant gate driver may include an additional voltage boosting capability that can be selectively enabled to compensate for a voltage drop during the signal transfer from the input to the output.

Abstract: A radio frequency filtering circuitry includes a first inductor, a second inductor, and a conductive loop. The first inductor receives a first current that induces a second current in the second inductor upon receiving the first current. The first inductor and/or the second inductor induce a third current in the conductive loop. The conductive loop adjusts the third current to reduce a first gain peak of an output signal to correlate to a second gain peak of the output signal.

Abstract: An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

Abstract: A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.

Abstract: The present disclosure provides a charge pump circuit. The power receiving terminal receives a power voltage. The first energy storage capacitor is coupled between the positive output terminal and the ground terminal. The second energy storage capacitor is coupled between the negative output terminal and the ground terminal. The charge pump circuit controls the first and the second flying capacitors to have a first and a second connection relation with the power-receiving, the ground and the positive and the negative output terminals respectively within a first and a second operation time in a double voltage power supplying mode. The charge pump circuit is operated in the first and the second operation time in an interlaced manner, such that the positive and the negative output terminals respectively output a positive and a negative output voltages each having a voltage value that is a double of that of the power voltage.

Abstract: An apparatus is disclosed for a single-inductor multiple-output (SIMO) power converter with a cross-regulation switch. An example apparatus includes a power source and a SIMO power converter. The SIMO power converter includes an input node coupled to the power source, a first node, a second node, a ground node, and an inductor coupled between the first node and the second node. The single-inductor multiple-output power converter also includes a first switch coupled between the input node and the first node, a second switch coupled between the first node and the ground node, and a cross-regulation switch coupled between the input node and the second node.

Abstract: A wireless power transmitter includes a power conversion unit configured to transfer wireless power to a wireless power receiver by forming magnetic coupling with the wireless power receiver; and a communication/control unit configured to communicate with the wireless power receiver to control transmission of the wireless power and to perform transmission or reception of data, wherein the communication/control unit further configured to set a target power level based on an operation condition, receive, from the wireless power receiver, a received power packet (RPP) which informs a value of the wireless power received by the wireless power receiver, transmit a bit pattern to the wireless power receiver in response to the RPP, the bit pattern requesting communication initiated by the wireless power transmitter, and receive, from the wireless power receiver, a response packet to allow the communication initiated by the wireless power transmitter.

Abstract: A power-on clear circuit includes a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit that operates on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit that outputs a power-on clear signal in accordance with an output of the second inverter unit.

Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

Abstract: An off chip driving system includes a decision circuit, multiple first and second adjustable-enhancement circuits, and multiple first and second drivers. The decision circuit outputs a first and a second decision signal according to a clock and an input data. Each first adjustable-enhancement circuit generates one of first control signals in response to the first and the second decision signal and one of first optional signals. Each second adjustable-enhancement circuit generates one of second control signals in response to the first and the second decision signal and one of second optional signals. Each first driver is coupled to the corresponding first adjustable-enhancement circuit and configured to be enabled in response to the corresponding first control signal. Each second driver is coupled to the corresponding second adjustable-enhancement circuit and configured to be enabled in response to the corresponding second control signal.

Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information.

Abstract: Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.