Abstract: A power transmitting apparatus that transmits power to a power receiving apparatus executes intermittent wireless transmission of power. The power transmitting apparatus operates according to one of a first power transmitting method including detecting a signal load-modulated by the power receiving apparatus using an ID in response to the transmitted power during the intermittent transmission and a second power transmitting method including transmitting the power having modulated the power according to an ID determined in advance so that the power receiving apparatus detects the ID determined in advance.

Abstract: A phase locked circuit includes an oscillator configured to generate an output clock signal, a first phase detector configured to detect a phase difference between an input clock signal and a feedback clock signal based on the output clock signal, a second phase detector having a wider phase locking range than that of the first phase detector and configured to detect the phase difference between the input clock signal and the feedback clock signal, and a charge pump controller configured to control an output current of a charge pump included in the second phase detector based on the phase difference detected by the first phase detector. When the phase difference between the input clock signal and the feedback clock signal is within the phase locking range of the first phase detector, the oscillator and the first phase detector are connected to each other.

Abstract: A vehicle electrical power system includes a phase module assembly of a multi-phase inverter. The phase module assembly includes first and second flat laminated busbars extending in orthogonal planes. The phase module assembly also includes one or more transistors that convert direct current into one phase of a multi-phase alternating current of the multi-phase inverter, and to output the phase of the multi-phase alternating current to the load. The phase module assembly also includes one or more capacitors conductively coupled with the internal positive and negative terminal connectors and with the external positive and negative bushings configured to be conductively coupled with the power source of direct current. The assembly can be useful for vehicles because the components of the system are configured to carry large amounts of current in a more reliable and sustainable manner.

Abstract: Aspects of the present disclosure provide for a method. In at least some examples, the method includes controlling a switch to decouple a first node at which a pull-up signal is present from a second node. The method further includes measuring and storing a value of the pull-up signal as a reference value. The method further includes controlling the switch to couple the first node at which the pull-up signal is present to the second node. The method further includes determining whether a pull-down signal is present at the second node by comparing the reference value to a value of a signal present at the second node.

Abstract: System, methods, and other embodiments described herein relate to managing electrical power delivery to a peripheral device in a vehicle. In one embodiment, a method includes, receiving, at a vehicle-side controller via a communication channel, a request from the peripheral device to modify the electrical power delivery to the peripheral device. The method includes, in response to identifying that the request is for an increase to the electrical power delivery, determining an electrical loading of the vehicle. The method also includes communicating a message over the communication channel to the peripheral device that causes the peripheral device to manage the electrical power delivery according to whether the electrical loading satisfies a loading threshold of the vehicle.

Abstract: The invention relates to a method for actuating at least one semiconductor switch, in particular in a component of a motor vehicle. The at least one semiconductor switch can be switched with a control voltage (1) according to the following method steps: a1) specifying the control voltage (1) in a tolerance range (2) and a2) monitoring whether a control voltage (1) actually being applied to the at least one semiconductor switch exceeds at least one threshold (4, 5), wherein at least the following method step is carried out at at least one control time: b1) ascertaining a difference between the control voltage (1) actually being applied to the at least one semiconductor switch and the at least one threshold, the control voltage (1) specified according to step a1) being manipulated according to the at least one control time using the result from step b1).

Abstract: Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.

Abstract: A PLL device includes a voltage control oscillation unit, an analog/digital converter, a quadrature demodulation unit, a comparison signal output unit, a phase difference detection unit, a loop filter, and a digital/analog converter. The quadrature demodulation unit quadrature-demodulates the digital feedback signal to obtain an in-phase component (I component) and a quadrature-phase component (Q component). The comparison signal has a set frequency of the output signal when the feedback signal is the output signal and has a frequency obtained by dividing the set frequency by the dividing number when the feedback signal is the frequency division signal. The phase difference detection unit obtains a phase difference between the digital feedback signal and the digital comparison signal based on the I component and the Q component of the digital feedback signal and the I component and an Q component of a comparison signal.

Abstract: The present invention is related to an apparatus and method for performing communication in a wireless power transfer system. The description discloses a wireless power transmitter including a communication/control unit configured to perform a negotiation for a first available power indicator with a wireless power reception apparatus; and a power conversion unit configured to transmit a wireless power to the wireless power reception apparatus by generating magnetic coupling in a primary coil according to the first available power indicator. The wireless power transmitter provides an effect that a wireless power transmission apparatus is available to obtain status and authority as a master/transmitter depending on a situation, and current ambient situation/environment is reflected in real time.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

Abstract: A delay locked-loop includes, in part, a phase/frequency detector responsive to a reference clock signal, a charge pump responsive to the phase/frequency detector, a variable delay line responsive to an output of the charge pump to cause a delay in the reference clock signal thereby to generate an internal clock signal, and a controlled delay line that includes a multitude of fixed delay cells. The controlled delay line causes the internal clock signal to be delayed by a delay across one of the multitude of fixed delay cells in response to the output of the charge pump. The controlled delay line generates the output clock signal of the delay-locked loop. The delay locked-loop may further include an overflow detector configured to cause the selection of one of the multitude of fixed delays in response to the output of the charge pump.

Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.

Abstract: Certain aspects of the present disclosure provide circuitry connecting an output of voltage reference circuitry powered by a relatively high voltage to an input of a voltage buffer configured to generate a voltage lower than the high voltage. The connecting circuitry prevents the high voltage from reaching the input of the voltage buffer. One example electronic circuit generally includes a voltage reference circuit configured to be powered by a relatively higher voltage, a buffer circuit configured to generate a relatively lower voltage as compared to the relatively higher voltage, and circuitry coupled between an output of the voltage reference circuit and an input of the buffer circuit, the circuitry being configured to prevent the higher voltage from reaching the input of the buffer circuit.

Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.

Abstract: A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

Abstract: In an embodiment, a method for wirelessly transferring power through a low-e window includes: causing a first current to flow through a transmitter coil disposed in a first outer surface of the low-e window, the first current having a first frequency; inducing, with the first current, a second current to flow through a receiver coil disposed in a second outer surface of the low-e window, the low-e window having a metal or metal oxide layer having a first thickness; generating a voltage based on the second current; and powering an electronic device coupled to the receiver coil with the generated voltage, where the first frequency is associated with a first skin depth of the metal or metal oxide layer, and where the first skin depth is larger than the first thickness.

Abstract: A gate driver circuit includes a gate driver and a sensing circuit. The gate driver is configured to generate an on-current during a plurality of turn-on switching events to drive a transistor, where a voltage across the transistor changes from a first value to a second value with a slope during the plurality of turn-on switching events, where the slope is of either an active type dependent on an amplitude of the on-current or a passive type. The sensing circuit determines whether the slope during a first turn-on switching event is the active type or the passive type, and regulates the amplitude of the on-current during a second turn-on switching event that is subsequent to the first turn-on switching event if the slope is the active type and to maintain the amplitude of the on-current as unchanged during the second turn-on switching event if the slope is the passive type.

Abstract: Power management for an integrated circuit. One example embodiment is a method of operating a portable audio device including: reading, by a supply controller, a logic speed measurement from a logic gate delay line, the supply controller and the logic gate delay line implemented on a semiconductor substrate; computing, by the supply controller, a speed margin based on the logic speed measurement; creating, by the supply controller, a value indicative of a modified voltage level, the creating based on the speed margin; and modifying, by a main voltage converter on the semiconductor substrate, an output voltage responsive to the value indicative of the modified voltage level.

Abstract: Aspects of the present disclosure are directed to circuitry to control a gate voltage. As may be implemented in accordance with one or more embodiments, a voltage level is controlled for a field effect transistor (FET) having a floating gate and a target operating voltage above which the FET would be overcharged and around which the FET has a nominal operating range. Pulse circuitry is configured to apply energy to the floating gate in pulses, in operation the applied energy being pulsed low relative to the gate's target operating voltage, and then being changed by adjusting successive pulses until the gate reaches the target operating voltage. A feedback circuit samples a voltage level of, and enables the pulse circuitry to apply pulsed energy to, the floating gate for directing operation of the FET based on the target operating voltage in the nominal operating range.