Abstract: A charge pump system including charge pump circuitry, a charge pump controller, and current limit circuitry. The charge pump circuitry has an input coupled to a supply input node and has an output for developing a drive voltage. The charge pump controller controls the charge pump circuitry to increase the drive voltage above a supply voltage provided to the supply input node. The current limit circuitry limits current through the charge pump circuitry to a limited current level that is less than a maximum current level during a current limit mode to reduce current spikes at the nodes of the charge pump system that may generate EMI. A current mirror may be used as the current limit circuitry to directly limit current through switches of the charge pump circuitry. The timing of the charge pump switches may also be modified such as inserting strategic delays to reduce the current spikes.

Abstract: A balun includes a first LC resonator, a second LC resonator, a third LC resonator, and a fourth LC resonator. The second LC resonator is magnetically coupled with the first LC resonator. The fourth LC resonator is magnetically coupled with the third LC resonator and electrically connected between a third terminal and a fourth terminal in parallel with the second LC resonator. Each of the first LC resonator and the second LC resonator has a resonant frequency that is a first resonant frequency. Each of the third LC resonator and the fourth LC resonator has a resonant frequency that is a second resonant frequency higher than the first resonant frequency.

Abstract: A bootstrap circuit including: a charge pump; a power unit including a bootstrap capacitor, wherein the bootstrap capacitor is charged using an output voltage of the charge pump; and a switch driver for generating a bootstrap signal based on a clock signal and an analog signal, wherein the analog signal is input to an analog switch, the switch driver for controlling the analog switch using the bootstrap signal, and including a first body switch connected between an input terminal and a body of the analog switch.

Abstract: An internal voltage generation circuit includes a counting operation control signal generation circuit and a drive control signal generation circuit. The counting operation control signal generation circuit compares a test internal voltage with a test reference voltage to generate a counting operation control signal in a test mode. The drive control signal generation circuit generates a drive adjustment signal whose logic level combination is adjusted according to the counting operation control signal in the test mode. In addition, the drive control signal generation circuit compares the test internal voltage with the test reference voltage in the test mode to generate a drive control signal for driving the test internal voltage.

Abstract: A shift register unit including a first node control circuit, a second node control circuit, an energy-storing circuit, a first voltage pull circuit, a second voltage pull circuit, and an output circuit. The first node control circuit is configured to transfer a reset signal at a reset signal terminal to a first node in response to the reset signal at the reset signal terminal being active. The second node control circuit is configured to transfer an inactive voltage at a first voltage terminal to the first node in response to a potential at a second node being active. The output circuit is configured to transfer a clock signal at a clock signal terminal to a signal output terminal in response to the potential at the second node being active.

Abstract: The present application relates to a sub-bandgap reference source circuit, which comprises a current mirror source, a first branch comprising a first BJT and a second branch comprising a second BJT, the first BJT having an emitter current density lower than an emitter current density of the second BJT, the first branch and the second branch being connected at a first node coupled to ground; a first voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between a base terminal of the first BJT and a second node, the second resistor being coupled to ground; a second voltage divider comprising first and second resistances coupled in series, the first resistance being coupled between the second node and a base terminal of the second BJT, the second resistance being coupled to the first node; and an output terminal coupled to the second node.

Abstract: A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.

Abstract: The disclosed embodiments relate to the design of a system that implements an up-conversion mixer. This system includes a regulator-based linearized transconductance (gm) stage, which converts a differential intermediate frequency (IF) voltage signal into a corresponding pair of IF currents. It also includes a pair of current mirrors, which duplicates the pair of IF currents into sources of a set of switching transistors. The set of switching transistors uses a differential local oscillator (LO) signal to gate the duplicated pair of IF currents to produce a differential radio frequency (RF) output signal. Finally, a combination of capacitors and/or inductors is coupled to common source nodes of the set of switching transistors to suppress higher order harmonics in an associated common source node voltage signal.

Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.

Abstract: A control circuit used in an integrated circuit device is described. The control circuit comprises a startup timer configured to generate a startup timing signal; a startup circuit configured to generate a startup control signal; and a switching element coupled between the startup circuit and a load; wherein the switching element applies the startup control signal to the load during a startup period associated with the startup timing signal. A method of controlling an operation of an integrated circuit device is also described.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.

Abstract: The present invention relates to resistance calibration and in particular to resistance calibration in the context of semiconductor integrated circuitry.

Abstract: Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.

Abstract: A clocked comparator includes an upper-side sampling latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal; a lower-side sampling latch configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; and a decision-arbitrating latch configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

Abstract: An apparatus and a method for multiplying a frequency of an input signal are provided. The apparatus may include a main differential device for converting the input signal into a first differential signal and a second differential signal, a first multiplying device for outputting a first signal obtained by multiplying a frequency of the first differential signal, a second multiplying device for outputting a second signal obtained by multiplying a frequency of the second differential signal, and a compositing device for outputting a third signal obtained by combining the first signal and the second signal to remove a fundamental frequency component.

Abstract: A source of environmental pollution is the burning of fuel by the transportation vehicles (e.g., cars, trucks). The use of electric vehicles (EVs) is perceived as an essential step towards better utilization of energy. Current EVs make use of an electric engine and a battery pack that provides energy to that engine. The technology of electric engines is well developed because of the common use of such engines in trains, submarines and industrial facilities. But, while the battery packs used in EVs have made a lot of progress in the last couple of years, these battery packs still have problems. These battery packs are expansive, heavy, and limited in the amount of energy that they can provide. This obstacle is a major factor that limits the use of EVs today in the mass market. Described herein is an improved EV battery pack system.

Abstract: Disclosed are a clock compensation circuit, a clock circuit and a microcontroller. The clock compensation circuit may include: a detection circuit, configured to detect a capacitance control parameter capable of affecting a clock frequency output by a clock circuit; and a control unit, connected with the detection circuit, and configured to adjust a capacitance value of a target capacitor in the clock circuit according to the capacitance control parameter detected by the detection circuit, so as to change the clock frequency output by the clock circuit. With the clock compensation circuit, the clock circuit and the microcontroller, the problem of large fluctuation of a clock frequency output by a clock circuit in the related art is solved.