Abstract: A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.

Abstract: A square wave generator includes a sawtooth wave generator for generating a sawtooth wave, and a convertor for generating a square wave based on the sawtooth wave. The sawtooth wave generator includes a capacitor and a switching unit connected parallel to each other. A first terminal of the capacitor is electrically coupled to a power source and the convertor, and a second terminal of the capacitor is grounded. The switching unit includes a trigger and a field-effect transistor. When a voltage of the first terminal of the capacitor is not less than a first threshold voltage of the trigger, the trigger is turned on to activate the field-effect transistor, the field-effect transistor is turned on to ground the first terminal of the capacitor, so that the capacitor discharges rapidly.

Abstract: A wireless communication device includes conventional components to permit a network communication link to be established with a wireless communication network. In addition, the wireless communication device includes a non-network short-range transceiver that detects the presence of other similarly equipped devices. When two such equipped devices come within proximity of each other, a direct non-network wireless communication link is established. The two devices exchange portions of profile data and each analyzed the received profile data. If a match occurs, a contact notification is generated. This permits the wireless communication device to act as an auto-detecting social network device that detects the proximity of other devices whose owners have a profile that matches the stored user preference data. Subsequent communication may occur in a conventional manner using the wireless network communication channels and web applications may also be used to gain additional information.

Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.

Abstract: A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.

Abstract: A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. One of several algorithms produce a specific predetermined sequence of pulses of varying width such that the voltage maintains maximally flat characteristics while the current delivered to the load from the system plant varies within a range bounded only by inductive element continuous conduction at the low power extreme and non-saturation of the inductor core at the high power extreme.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A pad driving circuit includes an output control circuit, a voltage pump circuit, a first buffer series, and a second buffer series. The output control circuit controls whether a pad circuit can pass an input signal, in which the output control circuit enables the pad circuit to output the input signal when an enable signal is asserted. The voltage pump circuit generates a negative supply voltage having voltage less than a zero volt. The first buffer series, electrically connected between the output control circuit and the pad circuit, drives the pad circuit with a positive supply voltage and the negative supply voltage from the voltage pump circuit. The second buffer series drives the pad circuit with a ground voltage and the positive supply voltage.

Abstract: Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.

Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.

Abstract: A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

Abstract: According to one general aspect, an output driver configured to drive output signals from a core device may include a voltage convertor, an output stage, and a biasing unit. In various embodiments, the output driver is configured to operate in either a core device voltage mode or a high voltage mode. In some embodiments, the voltage convertor may be configured to receive a pair of differential input signals from a core device, wherein a maximum voltage of the input signals is equivalent to a core device voltage, and convert the input signals to a pair of intermediate input signals. In one embodiment, when in high voltage mode, the maximum voltage of the intermediate input signals may be equivalent to a high voltage that is higher than the core device voltage.

Abstract: A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.

Abstract: According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.

Abstract: A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability.

Abstract: A digital programmable frequency divider is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), RSFQ D flip-flop and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of frequency division and the frequency divider selectively imparts a respective frequency division for any of 2n states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Abstract: There is provided a signal generating apparatus including: a multiphase oscillating portion for generating a number of base signals having the same frequency and a predetermined phase difference of which the signal level transitions between a first level and a second level, and where periods during which the signal level of any given base signal is at the first level and the signal level of the next base signal having the predetermined phase delay relative to the given base signal is at the first level overlap; and a transition time point changing portion for generating a pulse signal by changing the time point when each base signal transitions from the first level to the second level to a time point before the next base signal transitions from the second level to the first level.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.