Patents Examined by An T. Luu
  • Common mode tracking receiver
    Patent number: 8030983
    Abstract: A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: October 4, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xinghai Tang, Hector Sanchez
  • Differential signal generation circuit
    Patent number: 8018265
    Abstract: A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: September 13, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong Ju Kim, Hae Rang Choi, Ji Wang Lee, Jae Min Jang
  • Output slew-rate controlled interface and method for controlling the output slew-rate of an interface
    Patent number: 8013648
    Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: September 6, 2011
    Assignee: Himax Technologies Limited
    Inventors: Lieh-Chiu Lin, Chun-Yu Chiu
  • Programmable signal routing
    Patent number: 8013659
    Abstract: A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: September 6, 2011
    Assignee: Silicon Labs Spectra, Inc.
    Inventors: Aysel Yildiz Okyay, Tugba Demirci, Gregory Jon Richmond
  • Gate control circuit
    Patent number: 8008953
    Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: August 30, 2011
    Assignee: Silego Technology, Inc.
    Inventors: Thomas D. Brumett, Jr., Marcelo Martinez, John Othniel McDonald
  • Adaptive clock generators, systems, and methods
    Patent number: 8008961
    Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 30, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Garg, Chiaming Chai, Jeffrey Todd Bridges
  • Duty ratio control apparatus and duty ratio control method
    Patent number: 8004332
    Abstract: There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: August 23, 2011
    Assignee: Advantest Corporation
    Inventor: Masayuki Nakamura
  • Semiconductor integrated circuit and control signal distribution method
    Patent number: 7999594
    Abstract: A semiconductor integrated circuit includes a plurality of areas, each of which generates phase clocks in accordance with an external clock and control signals and performs a predetermined process assigned to each of the phase clocks. The semiconductor integrated circuit includes a control signal distributing unit that adjusts a timing at which the control signal is turned ON or OFF for each of the areas and distributes the adjusted control signals to the plurality of areas so that the plurality of areas do not perform a same process at a same timing.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Limited
    Inventor: Masato Susuki
  • High-voltage-tolerant linear scale-down circuit using low-voltage device
    Patent number: 7999598
    Abstract: A voltage scale down circuit includes an input node configured to receive a voltage input within an input voltage range. At least two voltage followers are coupled to the input node. The voltage scale down circuit also includes at least two scalers. Each scaler is coupled to a respective voltage follower. An output node is coupled to the at least two scalers. Each voltage follower is configured to receive the voltage input. Each voltage follower is configured to supply a respective voltage for the voltage input within a narrower portion of the input voltage range. The output node is configured to supply a voltage output linearly related to the voltage input. An output voltage range of the voltage output is narrower than the input voltage range.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Tsung-Hsin Yu
  • Enhanced predistortion for slewing correction
    Patent number: 7999587
    Abstract: The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle 5 modulation to the baseband signal as additional predistortion in response to the detected envelope information. Thereby, slewing distortions in the pulse-shaped signal are removed or at least reduced.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: August 16, 2011
    Assignee: ST-Ericsson SA
    Inventors: Jan S. Vromans, Jan C. A. Dekkers, Gerben W. De Jong
  • Pulse width modulation control system
    Patent number: 7990200
    Abstract: A PWM control system includes a multi-phase PWM controller and at least one single-phase PWM controller. The multi-phase PWM controller is capable of generating a multi-phase PWM signal. The at least one single-phase PWM controller is capable of generating a single-phase PWM signal. A phase difference between the single-phase PWM signal and the multi-phase signal is greater than 0 degree and less than 180 degree.
    Type: Grant
    Filed: September 20, 2009
    Date of Patent: August 2, 2011
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Shi-Tao Chen, Hsiang-Jui Hung, Sheng-Chung Huang, Kun-Lung Wu, Yi-Ping Li
  • Output driver circuit
    Patent number: 7986174
    Abstract: An output driver circuit includes a pre-driver unit and a first driving unit. The pre-driver unit is configured to generate a driving selection signal and a driving signal from a pre-driving signal in response to a group selection signal and a code signal. The first driving unit is configured to drive a data pad in response to the driving selection signal and the driving signal.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Kwon Lee
  • Delay line
    Patent number: 7982517
    Abstract: A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: July 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung-Hoon Kim
  • Precision phase generator and method for phase generation
    Patent number: 7977992
    Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: July 12, 2011
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventor: Michael Martin Farmer
  • Configurable pulse generator
    Patent number: 7977995
    Abstract: The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: July 12, 2011
    Assignee: Oracle America, Inc.
    Inventors: Robert P. Masleid, Anand Dixit
  • Pulse generator with precision edge placement
    Patent number: 7977996
    Abstract: A digital pulse generator including a fractional delay filter is provided as having a plurality of step response functions that can be selected on a sample by sample basis by selection of filter coefficients. The step response functions are all identical but each have different group delay. Responsive to an input waveform having leading and trailing edges aligned with a system clock, the fractional delay filter can output the impulse responses as a pulse waveform having respective leading and trailing edges delayed by different respective fractions of a signal clock cycle from the respective leading and trailing edges of the input waveform. The pulse waveform as output can thus have desired pulse width and desired period of repetition with finer edge placement resolution of improved accuracy.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Agilent Technologies, Inc.
    Inventors: David Paul Kjosness, Bryan D. Boswell
  • Signal delay circuit
    Patent number: 7977993
    Abstract: A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: July 12, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Hung-Wen Lu, Chau-Chin Su
  • Duty correction circuit, duty correction system, and duty correction method
    Patent number: 7977990
    Abstract: A duty correction circuit is provided which includes a level shifter receives complementary differential input signals having a duty ratio and controls levels of the differential input signals; a TrTf control circuit receives output signals of the level shifter and controls edge angles of the output signals; a waveform shaping circuit receives output signals of the TrTf control circuit and shapes waveforms of the output signals; a first common mode comparator extracts common modes of the output signals of the TrTf control circuit and compares the common modes; and a second common mode comparator extracts common modes of output signals of the waveform shaping circuit and compares the common modes. The level shifter controls the levels based on outputs of the first common mode comparator and the TrTf control circuit controls the edge angles based on outputs of the second common mode comparator.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 12, 2011
    Assignee: Fujitsu Limited
    Inventor: Satoshi Matsubara
  • Driver circuit
    Patent number: 7973585
    Abstract: A driver circuit including a pre-driver B1 that operates by receiving operating power from a first power supply VDDI, and a main-driver B2 that receives operating power from a second power supply VDDE, amplifies an output signal from the pre-driver B1, and outputs the amplified signal. It also includes a first switch B4 between the first power supply VDDI and the pre-driver B1. It also includes a second switch B5 between the second power supply VDDE and the main-driver B2. A overvoltage protection sequence circuit B3 controls the On/Off states of the first switch B4 and the second switch B5 to controls the On/Off order of the pre-driver B1 and the main-driver B2. By doing so, the overvoltage protection sequence circuit B3 prevent an overvoltage from being applied to the driver circuit, especially to the main-driver B2.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: July 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Satoru Kubo
  • High-performance memory interface circuit architecture
    Patent number: 7969215
    Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: June 28, 2011
    Assignee: Altera Corporation
    Inventors: Joseph Huang, Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian D. Johnson