Patents Examined by An T. Luu
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Patent number: 10224926Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.Type: GrantFiled: March 12, 2018Date of Patent: March 5, 2019Assignee: FLEXTRONICS AP, LLCInventor: Antony E. Brinlee
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Patent number: 10222818Abstract: A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.Type: GrantFiled: July 19, 2018Date of Patent: March 5, 2019Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 10217608Abstract: In one embodiment, a switching circuit includes a first switch coupled to a first switch terminal, the first switch comprising at least one gallium nitride high-electron mobility transistor (GaN HEMT); a second switch coupled in series with the first switch and a second switch terminal, the second switching comprising a GaN HEMT; and at least one power source configured to provide power to the first switch and the second switch; wherein the second switch is configured to drive the first switch ON and OFF.Type: GrantFiled: August 3, 2017Date of Patent: February 26, 2019Inventor: Anton Mavretic
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Patent number: 10218339Abstract: An integrated circuit device includes a substrate, a voltage monitor circuit formed on the substrate, and a trimming circuit formed on the substrate that includes a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit; a beta multiplier circuit having an input coupled to an output of the successive approximation register circuit, an output coupled to a first input of the voltage monitor circuit, and a variable resistance circuit. A resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.Type: GrantFiled: July 27, 2017Date of Patent: February 26, 2019Assignee: NXP USA, Inc.Inventors: Jae Woong Jeong, LeRoy Winemberg
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Patent number: 10218340Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.Type: GrantFiled: December 22, 2017Date of Patent: February 26, 2019Assignee: Micron Technology, Inc.Inventors: Hideyuki Ichida, Raghukiran Sreeramaneni
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Patent number: 10211726Abstract: Cross-coupled charge-pumps. At least some of the example embodiment are methods including: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump; refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge; electrically isolating the first through fourth capacitors during a dead time; and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump; and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors.Type: GrantFiled: August 22, 2018Date of Patent: February 19, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Pierre Genest
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Patent number: 10211834Abstract: A low-voltage-drop rectifier circuit includes a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a second MOSFET, a comparator, and a level adjustment circuit. The first MOSFET has a gate terminal for receiving a control voltage, a source terminal connected to a connection node, a drain terminal connected to an input node, and a body terminal connected to the connection node. The second MOSFET has a gate terminal for receiving the control voltage, a source terminal connected to an output node, a drain terminal connected to the connection node, and a body terminal connected to the output node. The comparator generates a first comparison voltage and a second comparison voltage according to an input voltage at the input node and an output voltage at the output node. The level adjustment circuit generates and fine-tunes the control voltage according to the first comparison voltage and the second comparison voltage.Type: GrantFiled: October 30, 2017Date of Patent: February 19, 2019Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventor: Yeong-Sheng Lee
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Patent number: 10211824Abstract: A semiconductor device includes a drive control circuit which drives a gate terminal of an IGBT. The drive control circuit includes a state machine control circuit, a base data memory and a current drive circuit which drives the IGBT on the basis of driving current information stored in the base data memory. The state machine control circuit reads out driving current information for rising stored in the base data memory a plurality of times in a predetermined time period and drives the current drive circuit at rising of a PWM signal, and reads out driving current information for falling stored in the base data memory a plurality of times in a predetermined time period and drives the current drive circuit at falling of the PWM signal.Type: GrantFiled: October 26, 2017Date of Patent: February 19, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Tsurumaru
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Patent number: 10193359Abstract: A source of environmental pollution is the burning of fuel by the transportation vehicles (e.g., cars, trucks). The use of electric vehicles (EVs) is perceived as an essential step towards better utilization of energy. Current EVs make use of an electric engine and a battery pack that provides energy to that engine. The technology of electric engines is well developed because of the common use of such engines in trains, submarines and industrial facilities. But, while the battery packs used in EVs have made a lot of progress in the last couple of years, these battery packs still have problems. These battery packs are expansive, heavy, and limited in the amount of energy that they can provide. This obstacle is a major factor that limits the use of EVs today in the mass market. Described herein is an improved EV battery pack system.Type: GrantFiled: October 26, 2015Date of Patent: January 29, 2019Assignee: EVchip Energy Ltd.Inventor: Avraham Ganor
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Patent number: 10177764Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.Type: GrantFiled: January 12, 2017Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Patent number: 10171033Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.Type: GrantFiled: March 25, 2017Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Khang Choong Yong, Raymond Chong, Ramaswamy Parthasarathy, Stephen Hall, Chin Lee Kuan
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Patent number: 10171069Abstract: The application discloses the control of switches, such as metal-oxide semiconductor field effect transistors (MOSFETs) devices, during surge events. The switch controllers and methods for operation thereof discuss methods for providing driving signals to the switch for adjusting the mode of operation based on the voltage and/or current thresholds as sensed by the system and/or by the switch controller.Type: GrantFiled: January 26, 2018Date of Patent: January 1, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Thomas Alois Zoels, Fabio Carastro
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Patent number: 10170164Abstract: Embodiments of the present disclosure provide a circuit structure including: a circuit driven by first and second sense amplifier (SA) output; a first driver having a first PMOS coupled to a node and to a pair of serially coupled NMOSs, wherein the first SA output is coupled to the first PMOS and the first NMOS of the first driver; a second driver having a second PMOS coupled to a node and a pair of coupled NMOSs, wherein the second SA output is coupled to the second PMOS and second NMOS of the second driver; a first and second supply PMOS, wherein first supply PMOS is coupled to the node of the first driver and to the second supply PMOS and first NMOS of the second driver, and wherein the second supply PMOS is coupled to node of second driver and to the first supply PMOS and second NMOS of first driver.Type: GrantFiled: February 13, 2018Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventor: Venkatraghavan Bringivijayaraghavan
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Patent number: 10158364Abstract: A circuit having a tracking loop and a realignment loop is disclosed. The circuit includes: a phase frequency detector (PFD) module for comparing a phase difference of a first input signal and a second input signal; a pump module for converting PFD phase error to charge, wherein the pump module further comprises a low pass filter (LPF); an adjustable realignment module for adjusting a realignment strength, the adjustable realignment module receives a first plurality of inputs from the PFD module, the adjustable realignment module transmits a second plurality of outputs to the pump module; and a ring oscillator unit, the ring oscillator unit receives a first input from the pump module and a second input from the adjustable realignment module, and based on the first and second inputs produces a feedback signal.Type: GrantFiled: January 29, 2018Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsien Tsai, Cheng-Hsiang Hsieh, Chih-Hsien Chang, Ruey-Bin Sheen
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Patent number: 10153696Abstract: Circuitry and methods for sampling a signal are disclosed. An example of the circuitry includes a node for coupling the circuitry to the signal being sampled and a plurality of capacitors, wherein each capacitor is selectively coupled to the node by a switch. An analog-to-digital converter is coupled to the node and is for measuring the voltages of individual ones of the plurality of capacitors and converting the voltages to digital signals. Delay circuitry is coupled to each of the switches, the delay circuitry is for closing one switch at a time for a predetermined period.Type: GrantFiled: July 25, 2017Date of Patent: December 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 10127952Abstract: A power control module comprising low voltage (LV) port for receiving low supply voltage via LV supply line, high voltage (HV) input port for receiving high supply voltage via HV supply line, wherein high supply voltage is higher than low supply voltage, LV output port for providing low output voltage, HV output port for providing high output voltage, LV node coupled to LV input port, HV node coupled to HV input port, bypass circuit coupled between LV and HV nodes, LV protection circuit coupled between LV node and LV output port, and control circuitry configured to detect power fault on either LV or HV supply line, isolate the LV and HV nodes from LV and HV supply lines, provide backup voltage to LV node, and cause LV protection circuit to regulate backup voltage at LV node to maintain low output voltage at LV output port to within predetermined operating range.Type: GrantFiled: February 14, 2018Date of Patent: November 13, 2018Assignee: Western Digital Technologies, Inc.Inventor: Ryan P. Mayo
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Patent number: 8120408Abstract: A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.Type: GrantFiled: July 14, 2008Date of Patent: February 21, 2012Assignee: Cypress Semiconductor CorporationInventors: Mohandas Palatholmana Sivadasan, Gajendar Rohilla
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Patent number: 8085067Abstract: A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node.Type: GrantFiled: December 21, 2006Date of Patent: December 27, 2011Assignee: Cypress Semiconductor CorporationInventor: Jonathon Stiff
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Patent number: 8081016Abstract: An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals.Type: GrantFiled: July 27, 2010Date of Patent: December 20, 2011Assignee: Hynix Semiconductor Inc.Inventor: Eun Ryeong Lee
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Patent number: 8072256Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.Type: GrantFiled: September 14, 2007Date of Patent: December 6, 2011Assignee: Mosaid Technologies IncorporatedInventor: Hong Beom Pyeon