Abstract: In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100V when an external voltage is applied between the first surface region and second surface region.

Abstract: A manufacturing method of a display including the following steps is provided. Firstly, a back plate, a first transfer platform and a second transfer platform are provided, wherein a plurality of first light-emitting devices are disposed on the first transfer platform, and a plurality of second light-emitting devices are disposed on the second transfer platform. Secondly, a plurality of first bonding layers are formed at a plurality of first positions of the back plate. Then, the first transfer platform and the back plate are correspondingly docked, so that the first light-emitting devices are bonded on the first positions through the first bonding layers. After that, a plurality of second bonding layers are formed at a plurality of second positions of the back plate. Finally, the second transfer platform and the back plate are correspondingly docked, so that the second light-emitting devices are bonded on the second positions through the second bonding layers.

Abstract: An optical member includes a first region and a second region constituting an interface with an adhesive member. The first region is disposed outside the second region in a second direction intersecting a first direction. An adhesive force generated at an interface between the first region and the adhesive member is smaller than an adhesive force generated at an interface between the second region and the adhesive member.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.

Abstract: Package structures and methods of forming the same are disclosed. A package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate in a first direction, and the at least one first integrated circuit and the at least one dummy substrate are separated by a distance in a second direction perpendicular to the first direction. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: Disclosed herein is a method of processing a workpiece having a plurality of streets provided on a face side thereof, the method including: a laser beam applying step of applying a laser beam having a wavelength that is transmittable through the workpiece along the streets while focusing the laser beam at a point within the workpiece, thereby forming modified layers in the workpiece along the streets and cracks extending from the modified layers to the face side; and a cutting step of, thereafter, cutting the workpiece from a reverse side thereof along the streets while supplying the workpiece with a cutting fluid, thereby removing the modified layers from the workpiece.

Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of the substrate. The method includes interposing dielectric layers between the amorphous semiconductor layers. The method includes forming polycrystalline semiconductor layers adjacent the amorphous semiconductor layers. The method includes interposing dielectric layers between the polycrystalline semiconductor layers and between the last amorphous semiconductor layer and the first polycrystalline semiconductor layer. The method includes forming a fine-grain polycrystalline semiconductor layer adjacent the polycrystalline semiconductor layers but is separated from the last polycrystalline semiconductor layer by an additional dielectric layer. The fine-grain polycrystalline semiconductor layer is formed at a higher temperature than the polycrystalline semiconductor layers and the amorphous semiconductor layers.

Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.

Abstract: The present invention relates to a method for manufacturing a nonvolatile memory thin film device by using a neutral particle beam generation apparatus. The present invention solves the problem that substrates such as glass and a plastic film may not be used for manufacturing the memory thin film device due to the high temperature heat treatment process for a long time, in the existing method for manufacturing the thin film device having the nonvolatile memory function by forming the mobile proton layer.

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: A semiconductor device includes a semiconductor die, an insulative layer, a conductive feature and a shield. The insulative layer surrounds the semiconductor die, and the insulative layer has a first surface and a second surface opposite to each other. The conductive feature is extended from the first surface to be proximal to the second surface of the insulative layer, and the conductive feature has a first end exposed by the first surface of the insulative layer. The shield covers the first surface of the insulative layer and is grounded through the first end of the conductive feature exposed by the first surface of the insulative layer.