Abstract: A method for manufacturing an optical semiconductor device, includes the steps of: forming a plurality of compound semiconductor layers including a sacrificial layer, an absorption layer, and a core layer; forming a first mesa from the plurality of compound semiconductor layers; forming an embedding layer that is a semiconductor layer having the first mesa embedded therein; after the step of forming the embedding layer, etching the sacrificial layer to form a chip including the plurality of compound semiconductor layers and the embedding layer; bonding the chip to a substrate comprising silicon and having a waveguide; and etching a portion of the first mesa of the chip bonded to the substrate to form a second mesa adjacent to the first mesa. The second mesa includes the core layer and is optically coupled to the waveguide of the substrate.

Abstract: The semiconductor apparatus includes: a thermal source TS including a semiconductor device generating heat in an operating state; a thermal diffusion unit thermally connected to the thermal source TS, the thermal diffusion unit including space in a direction opposite to the thermal source; a plurality of air-cooling fin units disposed in the space of the thermal diffusion unit, one end of the plurality of fin unit is connected to the thermal diffusion unit; and a base unit connected to the thermal diffusion unit, wherein the plurality of air-cooling fin units is connected to the base unit through a plurality of thermal contact units CP1, CP2, CP3, . . . , CPn. Provide is an air-cooling type semiconductor apparatus, power module, and power supply, each having high heat dissipation performance and realizing light weight.

Abstract: A light-emitting device includes a carrier, a light-emitting unit disposed on the carrier, a reflective element arranged on the light-emitting unit, and an optical element arranged on the carrier and surrounding the light-emitting unit.

Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

Abstract: In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.

Abstract: A display device include a light-emitting panel having first to third light-emitting diodes and a color panel on the light-emitting panel. The color panel includes first to third color areas that transmit light of different colors and a light-blocking area. The light-emitting panel includes two first power lines spaced apart from each other, connecting electrodes electrically connected to the two first power lines, and an insulating layer on the connecting electrodes, the insulating layer having openings each of which exposing a respective one of the connecting electrodes. The first light-emitting diode, the second light-emitting diode, and the third light-emitting diode are spaced apart from one another between the two first power lines. The second color area is smaller than each of the first color area and the third color area in size. The second color area is disposed between the first color area and the third color area.

Abstract: The present disclosure provides a light detecting device. The light detecting devices includes an insulating layer, a silicon layer, a light detecting layer, N first doped regions and M second doped regions. The silicon layer is disposed over the insulating layer. The light detecting layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The first doped regions have a first dopant type and are disposed within the light detecting layer. The second doped regions have a second dopant type and are disposed within the light detecting layer. The first doped regions and the second doped regions are alternatingly arranged. M and N are integers equal to or greater than 2.

Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor module includes: an upper arm module including a semiconductor chip; and a lower arm module including a semiconductor chip. The lower arm module is provided with: a facing section in which a lead frame and a lead frame each having a strip shape are disposed such that a main surface of the lead frame and a main surface of the lead frame face each other; and a non-facing section in which the lead frame and the lead frame are disposed such that the main surface of the lead frame and the main surface of the lead frame do not face each other.

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract: A waveguide photoelectric detector, comprising: a substrate comprising a silicon layer, the silicon layer having a silicon waveguide formed thereon; an active layer dispose on the silicon waveguide, the active layer having a first doped region formed thereon; a horizontal PIN junction formed at an area of the silicon layer below the active layer, the horizontal PIN junction comprising a second doped region, an intrinsic region, and a third doped region. A doping type of the second doped region is the same as that of the first doped region. One end of the second doped region near the intrinsic region is connected to the first doped region. The third doped region and the first doped region form a vertical PIN junction.

Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.

Abstract: A nano-structure layer is disclosed. The nano-structure layer includes an array of nano-structure material configured to receive a first light beam at a first angle of incidence and to emit the first light beam at a second angle greater than the first angle, the nano-structure material each having a largest dimension of less than 1000 nm.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

Abstract: Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants.

Abstract: Single-layer CNT composites and multilayered or multitiered structures formed therefrom, by stacking of vertically aligned carbon nanotube (CNT) arrays, and methods of making and using thereof are described herein. Such multilayered or multitiered structures can be used as thermal interface materials (TIMs) for a variety of applications, such as burn-in testing.

Abstract: The present disclosure relates to a photosensitive component, a detection substrate and a method for manufacturing the detection substrate. The photosensitive component includes: a first electrode layer, a photoelectric conversion layer, a second electrode layer, an insulating layer and a reflective layer. The photoelectric conversion layer is located on the first electrode layer. The second electrode layer is located on a surface of the photoelectric conversion layer away from the first electrode layer. The insulating layer covers side surfaces of the photoelectric conversion layer and at least a part of a surface of the second electrode layer away from the photoelectric conversion layer, and the insulating layer includes a transparent material. The reflective layer covers the insulating layer, and the reflective layer is configured to reflect at least a part of light entering the insulating layer to the side surfaces of the photoelectric conversion layer.

Abstract: A double-sided display panel and a method for manufacturing the same are provided. The double-sided display panel includes: a first substrate; a second substrate opposite to first substrate; a first display unit between the first substrate and the second substrate, the first display unit including a first luminescent layer and a first reflective layer which is closer to the second substrate than the first luminescent layer, wherein at least a part of light emitted from the first luminescent layer is reflected by the first reflective layer and emitted out through the first substrate; and a second display unit between the first substrate and second substrate, including a second luminescent layer, wherein light emitted from the second luminescent layer is emitted out through the second substrate. The first display unit includes a transparent electrode and a conductive contact layer which electrically connects the transparent electrode with the first reflective layer.

Abstract: A method for forming semiconductor devices from a semiconductor wafer includes cutting a first surface of a semiconductor wafer to form a first region that extends partially through the semiconductor wafer and the first region has a bottom portion. The method further includes directing a beam of laser light to the semiconductor wafer such that the beam of laser light is focused within the semiconductor wafer between the first surface and the second surface thereof and the beam of laser light further cuts the semiconductor wafer by material ablation to form a second region aligned with the first region. A resulting semiconductor device is disclosed as well.