Abstract: A semiconductor layer formed on a clad layer and a light absorbing layer formed on the semiconductor layer are provided. The semiconductor layer includes a p-type region and an n-type region. The p-type region, which is of p-type, is provided on a side of one side portion of the light absorbing layer in a direction perpendicular to a direction in which light is guided, and the n-type region, which is of n-type, is provided on a side of another side portion of the light absorbing layer in the direction perpendicular to the direction in which light is guided. A p-type contact layer, which is of p-type, is formed on the p-type region, and an n-type contact layer is formed on the n-type region.

Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.

Abstract: A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Abstract: Examples of the present technology include semiconductor processing methods that provide a substrate in a substrate processing region of a substrate processing chamber, where the substrate is maintained at a temperature less than or about 50° C. An inert precursor and a hydrocarbon-containing precursor may be flowed into the substrate processing region of the substrate processing chamber, where a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor may be greater than or about 10:1. A plasma may be generated from the inert precursor and the hydrocarbon-containing precursor, and a carbon-containing material may be deposited from the plasma on the substrate. The carbon-containing material may include diamond-like-carbon, and may have greater than or about 60% of the carbon atoms with sp3 hybridized bonds.

Abstract: An optoelectronic semiconductor component may have a semiconductor body comprising a first region of an n-type conductivity, a second region of a p-type conductivity, an active region capable of generating electromagnetic radiation, a marker layer, a plurality of emission regions and a plurality of recesses. The active region is disposed between the first region and the second region in a plane parallel to the main extension plane of the semiconductor body. The recesses delimit the emission regions in lateral direction. Starting from the side of the first region facing away from the active region, the recesses extend transversely to the main plane of the semiconductor body in the direction of the second region and adjoin the marker layer or penetrate the marker layer completely. The recesses are formed only in the first region or the recesses extend into the second region and completely penetrate the active region.

Abstract: Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends.

Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure. The test structure is disposed on the wafer, and includes a first device and a second device. The first device includes a first source/drain layer and a first gate layer disposed above the first source/drain layer. The second device includes a second source/drain layer and a second gate layer disposed above the second source/drain layer. The second gate layer is connected to the first gate layer. The first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

Abstract: A method for manufacturing an optical semiconductor device, includes the steps of: forming a plurality of compound semiconductor layers including a sacrificial layer, an absorption layer, and a core layer; forming a first mesa from the plurality of compound semiconductor layers; forming an embedding layer that is a semiconductor layer having the first mesa embedded therein; after the step of forming the embedding layer, etching the sacrificial layer to form a chip including the plurality of compound semiconductor layers and the embedding layer; bonding the chip to a substrate comprising silicon and having a waveguide; and etching a portion of the first mesa of the chip bonded to the substrate to form a second mesa adjacent to the first mesa. The second mesa includes the core layer and is optically coupled to the waveguide of the substrate.

Abstract: The semiconductor apparatus includes: a thermal source TS including a semiconductor device generating heat in an operating state; a thermal diffusion unit thermally connected to the thermal source TS, the thermal diffusion unit including space in a direction opposite to the thermal source; a plurality of air-cooling fin units disposed in the space of the thermal diffusion unit, one end of the plurality of fin unit is connected to the thermal diffusion unit; and a base unit connected to the thermal diffusion unit, wherein the plurality of air-cooling fin units is connected to the base unit through a plurality of thermal contact units CP1, CP2, CP3, . . . , CPn. Provide is an air-cooling type semiconductor apparatus, power module, and power supply, each having high heat dissipation performance and realizing light weight.

Abstract: A light-emitting device includes a carrier, a light-emitting unit disposed on the carrier, a reflective element arranged on the light-emitting unit, and an optical element arranged on the carrier and surrounding the light-emitting unit.

Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

Abstract: In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.

Abstract: A display device include a light-emitting panel having first to third light-emitting diodes and a color panel on the light-emitting panel. The color panel includes first to third color areas that transmit light of different colors and a light-blocking area. The light-emitting panel includes two first power lines spaced apart from each other, connecting electrodes electrically connected to the two first power lines, and an insulating layer on the connecting electrodes, the insulating layer having openings each of which exposing a respective one of the connecting electrodes. The first light-emitting diode, the second light-emitting diode, and the third light-emitting diode are spaced apart from one another between the two first power lines. The second color area is smaller than each of the first color area and the third color area in size. The second color area is disposed between the first color area and the third color area.

Abstract: The present disclosure provides a light detecting device. The light detecting devices includes an insulating layer, a silicon layer, a light detecting layer, N first doped regions and M second doped regions. The silicon layer is disposed over the insulating layer. The light detecting layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The first doped regions have a first dopant type and are disposed within the light detecting layer. The second doped regions have a second dopant type and are disposed within the light detecting layer. The first doped regions and the second doped regions are alternatingly arranged. M and N are integers equal to or greater than 2.

Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor module includes: an upper arm module including a semiconductor chip; and a lower arm module including a semiconductor chip. The lower arm module is provided with: a facing section in which a lead frame and a lead frame each having a strip shape are disposed such that a main surface of the lead frame and a main surface of the lead frame face each other; and a non-facing section in which the lead frame and the lead frame are disposed such that the main surface of the lead frame and the main surface of the lead frame do not face each other.

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract: A waveguide photoelectric detector, comprising: a substrate comprising a silicon layer, the silicon layer having a silicon waveguide formed thereon; an active layer dispose on the silicon waveguide, the active layer having a first doped region formed thereon; a horizontal PIN junction formed at an area of the silicon layer below the active layer, the horizontal PIN junction comprising a second doped region, an intrinsic region, and a third doped region. A doping type of the second doped region is the same as that of the first doped region. One end of the second doped region near the intrinsic region is connected to the first doped region. The third doped region and the first doped region form a vertical PIN junction.