Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.

Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.

Abstract: A light-emitting device includes a substrate, a plurality of bumps over the substrate; and a plurality of light-emitting units separated by the bumps. Each of the light-emitting units includes a first electrode on the substrate, an organic layer on the first electrode, and a second electrode on the organic layer. The light-emitting units comprise a first light-emitting unit and a second light-emitting unit, and the first light-emitting unit further includes an intermediate layer between the organic layer and the second electrode. The organic layer of the first light-emitting unit includes a first material, the second electrodes of the first light-emitting unit and the second light-emitting unit include an electrode material, and the intermediate layer of the first light-emitting unit includes the first material and the electrode material.

Abstract: Example embodiments relate to single-photon avalanche diode detector (SPAD) arrays. One embodiment includes a SPAD array that includes a silicon substrate, a plurality of primary electrodes, and a plurality of secondary electrodes. Each of the primary electrodes includes a semiconductor material of a first doping type, extends in the silicon substrate in a first direction, and has a rotationally symmetric cross-section in a first plane perpendicular to the first direction. The plurality of secondary electrodes includes a semiconductor material of a second doping type and extends parallel to the primary electrodes in the silicon substrate. Further, the silicon substrate includes a doped upper field redistribution layer, a doped lower field redistribution layer, and a doped depletion layer arranged between the upper field redistribution layer and the lower field redistribution layer.

Abstract: The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic sites on the surface portion; dosing, at a temperature below 100 K, the surface portion using a gas with molecules comprising the dopant atom and hydrogen atoms in a manner such that, a portion of the molecules bonds to the surface portion; and incorporating one or more dopant atoms in a respective lithographic site by transferring an amount of energy to the dopant atoms. The number of dopant atoms incorporated in a lithographic site is deterministic and related to the size of the lithographic site.

Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.

Abstract: A display apparatus may include a metal substrate, an electroluminescence display panel, including a first contact hole and a base voltage pad adjacent to the first contact hole, on the metal substrate, a first adhesive member, including a second contact hole exposing at least a portion of the base voltage pad, on the electroluminescence display panel, and a conductive filler, filled in the first contact hole and the second contact hole, electrically connecting the metal substrate and the base voltage pad.

Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.

Abstract: A base support plate includes a support plate body. A support surface of the support plate body is configured to support a flexible base of a flexible display panel. The base support plate further includes a plurality of micro-structures disposed on the support surface of the support plate body, and the plurality of micro-structures are configured to diffuse incident light and transmit the incident light to the flexible base.

Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.

Abstract: A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.

Abstract: A method for producing a solar panel includes producing a tile. Producing the tile includes bonding an electrical insulation layer and a front face sheet layer together to produce a front portion of a substrate. Producing the tile also includes bonding the front portion of the substrate and a cell together. Producing the tile also includes bonding the front portion of the substrate and a wire together. The method also includes bonding a honeycomb core layer and a back face sheet layer to produce a back portion of the substrate. The method also includes bonding the tile and the back portion of the substrate together to produce the solar panel.

Abstract: Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processor, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processor is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processor. The buffer device is disposed on the data processor. The thermally conductive shield covers the data processor, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processor.

Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.