Abstract: An electroluminescent device including an anode and a cathode facing each other, an emission layer disposed between the anode and the cathode, the emission layer including quantum dots, a hole auxiliary layer disposed between the emission layer and the anode and an electron auxiliary layer disposed between the emission layer and the cathode, wherein the electroluminescent device is configured such that electrons are dominant in the emission layer and a logarithmic value (log (HT/ET)) of a hole transport capability (HT) relative to an electron transport capability (ET) is less than or equal to about ?1, or the electroluminescent device is configured such that holes are dominant in the emission layer and the logarithmic log value (log (HT/ET)) of the hole transport capability (HT) relative to the electron transport capability (ET) is greater than or equal to about 0.5.

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

Abstract: In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: A semiconductor substrate (1) having an active region (2) and a first surface and a second surface facing each other. A first type of passivating layer (5) is present for providing an electrical contact of a first conductivity type on a part of the first surface of the semiconductor substrate (1). A dielectric layer (4) is provided between the first type of passivating layer (5) and an active region (2) of the semiconductor substrate (1). Doping of the first conductivity type is provided in a layer (3) of the active region (2) of the semiconductor substrate (1) near the first surface. The lateral dopant level in the layer (3) of the active region (2) near the first surface is substantially uniform.

Abstract: III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

Abstract: A package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region.

Abstract: Memory devices having optical I/O interfaces are described herein. In one embodiment, a memory device includes a plurality of memories coupled to a substrate, each memory including one or more photon integrated (PIC) chips for converting electrical signals to/from optical signals. The memory device can further include a plurality of optical fibers, wherein individual ones of the memories are optically coupled to at least one of the optical fibers. The memories can receive/transmit the optical signals over the optical fibers and can be electrically coupled to a power supply/ground via the substrate.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A method for forming an electronic device comprising a first transistor and a second transistor, from a stack of layers comprising an isolating layer surmounted on an active layer made of a semi-conductive material, the method comprising at least the following steps: Forming an isolating trench to define, in the active layer, at least one first active region and at least one second active region, said isolating trench protruding with respect to the active layer of the second active region; Forming a masking layer without covering the active layer of the second active region and without covering a portion of the isolating trench; Etching: of a portion of the thickness of the active layer of the second active region, and of at least one portion of the thickness of said portion of the isolating trench.

Abstract: A method of manufacturing an inverted metamorphic multijunction solar cell by providing a growth semiconductor substrate with a top surface having a doping in the range of 1×1018 to 1×1020 charge carriers/cm3; depositing a window layer for a top (light facing) subcell subsequently to be formed directly on the top surface of the growth substrate; depositing a sequence of layers of semiconductor material forming a solar cell directly on the window layer; providing a surrogate substrate on the top surface of the sequence of layers of semiconductor material, and removing a portion of the semiconductor substrate so that only the high doped surface portion of the substrate, having a thickness in the range of 0.5 ?m to 10 ?m, remains.

Abstract: A laminated structure is provided. The laminated structure includes a light-emitting layer including a light emitting diode. The laminated structure also includes a first layer including a first thin film transistor circuit. The laminated structure further includes a second layer including a second thin film transistor circuit. The second layer is located between the light-emitting layer and the first layer. The second thin film transistor circuit includes a channel region. The light emitting diode is at least partially overlapped with the first thin film transistor circuit and not overlapped with the channel region of the second thin film transistor circuit in a top view direction of the laminated structure.

Abstract: A peeling method for peeling off a substrate provided over a support plate through a peel layer from the support plate includes: a first holding step of holding one of the support plate and the substrate by a first holding unit; a start point region forming step of blowing a fluid to an end portion of the peel layer exposed at an end portion of the support plate and the substrate, to form a start point region which will serve as a start point when peeling off the substrate from the support plate; a second holding step of holding the other of the support plate and the substrate by a second holding unit; and a peeling step of relatively moving the first holding unit and the second holding unit in directions for spacing away from each other, to peel off the substrate from the support plate.

Abstract: An encapsulation method for a flip chip that includes electroforming metal on an electrode surface of a flip chip and a surface of an encapsulation substrate simultaneously. The encapsulation method specifically includes setting an encapsulation substrate around a flip chip; plating a metal conducting film on an electrode surface of the flip chip and a surface of the encapsulation substrate; coating a photoresist on a surface of the metal conducting film; aligning and photoetching an electrode structure on a photoetching plate and an electrode structure of the flip chip, and covering an insulating part between electrodes with the photoresist; taking the metal conducting film as the electrode, electroforming metal inside the photoresist structural model; and removing the photoresist covering the insulating part and removing the metal conducting film. The encapsulation method adopts electroforming and photoetching technology, and thus the process is simplified and the production efficiency is improved.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

Abstract: Embodiments provide a patterning process. A photoresist layer is patterned. At least portions of the photoresist layer are converted from an organic material to an inorganic material by a deposition process of a metal oxide. All or some of the patterned photoresist layer may be converted to a carbon-metal-oxide. A metal oxide crust may be formed over the patterned photoresist layer. After conversion, the patterned photoresist layer is used as an etch mask to etch an underlying layer.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines.